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參數(shù)資料
| 型號(hào)： | LFXP20E-5FN484C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 中文描述： | FPGA, 2464 CLBS, PBGA484 |
| 封裝： | 23 X 23 MM, LEAD FREE, FPBGA-484 |
| 文件頁數(shù)： | 50/130頁 |
| 文件大?。?/td> | 1312K |
| 代理商： | LFXP20E-5FN484C |
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2-23
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Figure 2-28. LatticeXP Banks
LatticeXP devices contain two types of sysIO buffer pairs.
1.
Top and Bottom sysIO Buffer Pair (Single-Ended Outputs Only)
The sysIO buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and
two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also be
configured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
Only the I/Os on the top and bottom banks have PCI clamps. Note that the PCI clamp is enabled after VCC,
VCCAUX and VCCIO are at valid operating levels and the device has been configured.
2.
Left and Right sysIO Buffer Pair (Differential and Single-Ended Outputs)
The sysIO buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The refer-
enced input buffer can also be configured as a differential input. In these banks the two pads in the pair are
described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O,
and the comp (complementary) pad is associated with the negative side of the differential I/O.
Select I/Os in the left and right banks have LVDS differential output drivers. Refer to the Logic Signal Connec-
tions tables for more information.
V
REF1(2)
GND
Bank
2
V
CCIO2
V
REF2(2)
V
REF1(3)
GND
Bank
3
V
CCIO3
V
REF2(3)
V
REF1(7)
GND
Bank
7
V
CCIO7
V
REF2(7)
V
REF1(6)
GND
Note: N and M are the maximum number of I/Os per bank.
Bank
6
V
CCIO6
V
REF2(6)
V
REF1(5)
GND
Bank 5
V
CCIO5
V
REF2(5)
V
REF1(4)
GND
Bank 4
V
CCIO4
V
REF2(4)
V
REF1(
0)
GND
Bank 0
V
CCIO0
V
REF2(
0)
V
REF1(1)
GND
Bank 1
V
CCIO1
V
REF2(1)
1
M
1
M
1
M
1
M
1N
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