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參數(shù)資料
| 型號(hào)： | LFXP15C-4FN256C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 中文描述： | FPGA, 1932 CLBS, PBGA256 |
| 封裝： | 17 X 17 MM, LEAD FREE, FPBGA-256 |
| 文件頁數(shù)： | 55/130頁 |
| 文件大?。?/td> | 1312K |
| 代理商： | LFXP15C-4FN256C |
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2-27
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
Figure 2-29 provides a pictorial representation of the different programming ports and modes available in the Lattic-
eXP devices.
On power-up, the FPGA SRAM is ready to be configured with the sysCONFIG port active. The IEEE 1149.1 serial
mode can be activated any time after power-up by sending the appropriate command through the TAP port.
Leave Alone I/O
When using 1532 mode for non-volatile memory programming, users may specify I/Os as high, low, tristated or
held at current value. This provides excellent flexibility for implementing systems where reprogramming occurs on-
the-fly.
TransFR (Transparent Field Reconfiguration)
TransFR (TFR) is a unique Lattice technology that allows users to update their logic in the field without interrupting
system operation using a single ispVM command. See Lattice technical note #TN1087, Minimizing System Inter-
ruption During Configuration Using TransFR Technology, for details.
Security
The LatticeXP devices contain security bits that, when set, prevent the readback of the SRAM configuration and
non-volatile memory spaces. Once set, the only way to clear security bits is to erase the memory space.
For more information on device configuration, please see details of additional technical documentation at the end
of this data sheet.
Figure 2-29. ispXP Block Diagram
Internal Logic Analyzer Capability (ispTRACY)
All LatticeXP devices support an internal logic analyzer diagnostic feature. The diagnostic features provide capabil-
ities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace mem-
ory. This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at compile
time.
For more information on ispTRACY, please see information regarding additional technical documentation at the
end of this data sheet.
Oscillator
Every LatticeXP device has an internal CMOS oscillator which is used to derive a master serial clock for configura-
tion. The oscillator and the master serial clock run continuously in the configuration mode. The default value of the
ISP 1149.1 TAP Port
sysCONFIG Peripherial Port
BACKGND
1532
sysCONFIG
SRAM
Memory Space
Configure in milliseconds
Program in seconds
Download in microseconds
Power-up
Refresh
Port
Mode
Memory Space
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFXP15C-4FN256I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 15.4K LUTs 188 IO 1. 8/2.5/3.3V-4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP15C-4FN388C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 15.4K LUTs 268 IO 1. 8/2.5/3.3V -4 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP15C-4FN388I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 15.4K LUTs 268 IO 1. 8/2.5/3.3V-4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP15C-4FN484C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 15.4K LUTs 1.8/2.5/3 .3V -4 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP15C-4FN484I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 15.4K LUTs 1.8/2.5/3 .3V-4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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