Figure 2-32. DQS Local Bus. Figure 2-33. DLL Calibration Bus and DQS/DQS Transition Distri" />
參數(shù)資料
型號: LFECP33E-5FN672C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 88/163頁
文件大小: 0K
描述: IC FPGA 32.8KLUTS 672FPBGA
產(chǎn)品培訓(xùn)模塊: LatticeECP3 Introduction
標(biāo)準(zhǔn)包裝: 40
系列: ECP
邏輯元件/單元數(shù): 32800
RAM 位總計: 434176
輸入/輸出數(shù): 496
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 672-BBGA
供應(yīng)商設(shè)備封裝: 672-FPBGA(27x27)
2-27
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-32. DQS Local Bus.
Figure 2-33. DLL Calibration Bus and DQS/DQS Transition Distribution
DI
CLKI
CEI
PIO
GSR
DQS
Input
Register Block
( 5 Flip Flops)
To Sync.
Reg.
DQS
To DDR
Reg.
DQS
Strobe
PAD
DDR
Datain
PAD
sysIO
Buffer
DI
sysIO
Buffer
PIO
DQSDEL
Polarity Control
Logic
DQS
Calibration Bus
from DLL
Delay
Control
Bus
Polarity
Control
Bus
DQS
Bus
DLL
Polarity Control Bus
DQS Bus
Delay Control Bus
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