- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗4562 > LFECP33E-5FN672C (Lattice Semiconductor Corporation)IC FPGA 32.8KLUTS 672FPBGA PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | LFECP33E-5FN672C |
| 寤犲晢锛� | Lattice Semiconductor Corporation |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 82/163闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FPGA 32.8KLUTS 672FPBGA |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | LatticeECP3 Introduction |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 40 |
| 绯诲垪锛� | ECP |
| 閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 32800 |
| RAM 浣嶇附瑷�(j矛)锛� | 434176 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 496 |
| 闆绘簮闆诲锛� | 1.14 V ~ 1.26 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 85°C |
| 灏佽/澶栨锛� | 672-BBGA |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 672-FPBGA锛�27x27锛� |
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2-22
Architecture
LatticeECP/EC Family Data Sheet
Table 2-12. PIO Signal List
Figure 2-25. DQS Routing
PIO
The PIO contains four blocks: an input register block, output register block, tristate register block and a control logic
block. These blocks contain registers for both single data rate (SDR) and double data rate (DDR) operation along
with the necessary clock and selection logic. Programmable delay lines used to shift incoming clock and data sig-
nals are also included in these blocks.
Name
Type
Description
CE0, CE1
Control from the core
Clock enables for input and output block FFs.
CLK0, CLK1
Control from the core
System clocks for input and output blocks.
LSR
Control from the core
Local Set/Reset.
GSRN
Control from routing
Global Set/Reset (active low).
INCK
Input to the core
Input to Primary Clock Network or PLL reference inputs.
DQS
Input to PIO
DQS signal from logic (routing) to PIO.
INDD
Input to the core
Unregistered data input to core.
INFF
Input to the core
Registered input on positive edge of the clock (CLK0).
IPOS0, IPOS1
Input to the core
DDRX registered inputs to the core.
ONEG0
Control from the core
Output signals from the core for SDR and DDR operation.
OPOS0,
Control from the core
Output signals from the core for DDR operation
OPOS1 ONEG1
Tristate control from the core
Signals to Tristate Register block for DDR operation.
TD
Tristate control from the core
Tristate signal from the core used in SDR operation.
DDRCLKPOL
Control from clock polarity bus
Controls the polarity of the clock (CLK0) that feed the DDR input block.
PIO A
PIO B
PADA "T"
PADB "C"
PIO B
PIO A
PIO B
PIO A
Assigned
DQS Pin
DQS
sysIO
Buffer
LVDS Pair
PADA "T"
PADB "C"
LVDS Pair
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
PIO A
PIO B
PADA "T"
PADB "C"
LVDS Pair
Delay
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| 93LC56BT-I/OT | IC EEPROM 2KBIT 3MHZ SOT23-6 |
| 24LC04BT-I/OT | IC EEPROM 4KBIT 400KHZ SOT23-5 |
| 93C46BT/SN | IC EEPROM 1KBIT 2MHZ 8SOIC |
| AMM25DSEI-S243 | CONN EDGECARD 50POS .156 EYELET |
| HCC65DRXS-S734 | CONN EDGECARD 130PS DIP .100 SLD |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| LFECP33E-5FN672I | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū:Lattice Semiconductor 鍔熻兘鎻忚堪:LatticeECP/EC Family Data Sheet |
| LFECP33E-5Q208C | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū:Lattice Semiconductor 鍔熻兘鎻忚堪:LatticeECP/EC Family Data Sheet |
| LFECP33E-5Q208I | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū:Lattice Semiconductor 鍔熻兘鎻忚堪:LatticeECP/EC Family Data Sheet |
| LFECP33E-5QN208C | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū:Lattice Semiconductor 鍔熻兘鎻忚堪:LatticeECP/EC Family Data Sheet |
| LFECP33E-5QN208I | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū:Lattice Semiconductor 鍔熻兘鎻忚堪:LatticeECP/EC Family Data Sheet |
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