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參數(shù)資料
| 型號(hào)： | LC89058W-E |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, SQFP-48 |
| 文件頁數(shù)： | 33/46頁 |
| 文件大?。?/td> | 284K |
| 代理商： | LC89058W-E |
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LC89058W-E
No.A1056-39/64
12.1.2 CCB interface
The CCB interface is a SANYO’s original serial bus format based on LSB-first communication, but three-state is
employed instead of open-drain for the data output format of LC89058W-E.
Data input/output is performed following CCB address input. The same CCB address cannot be used for both read and
write operation.
Table 12.2 Relationship between Register I/O Contents and CCB Addresses
Register I/O contents
R/W
CCB address
B0
B1
B2
B3
A0
A1
A2
A3
Function setting data input
Write
0xE8
0
1
0
1
Input detection, interrupt output
Read
0xEA
0
1
0
1
0
1
fs data output
Read
0xEB
1
0
1
0
1
CS data output
Read
0xEC
0
1
0
1
Pc data output
Read
0xED
1
0
1
0
1
12.1.3 Data write procedure
Input is performed in the following sequence: CCB addresses of A0 to A3 and B0 to B3, chip addresses of DI0 and
DI1, command addresses of DI4 to DI7, and data of DI8 to DI15. DI2 and DI3 are reserved for the system. So, DI2
and DI3 input must be doing "0".
For the chip addresses, DI0 corresponds to CAL (low-order), and DI1 to CAU (high-order). For details, see section 9.2.
12.1.4 Data read procedure
Read data is output from DO. DO is in the high impedance state when CE is "L", and begins outputting from the rising
edge of CE after output setting is established at the CCB address. DO then returns to the high impedance state at the
falling edge of CE.
If DO outputs are shared using multiple LC89058W-E units, it is possible to set the DO outputs of the LC89058W-E
units of which data is not to be read to be always in the high impedance state with DOEN. With this setting, only the
targeted outputs can be read.
12.1.5 Points to notices when normal H clock is used
The CCB interface uses CL of a normal L clock, and it is also possible to use CL of a normal H clock. However, input
the clock based on CCB microcontroller interface AC characteristics.
CL is lowered before CE is raised when data reads.
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