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參數(shù)資料
| 型號： | LC89058W-E |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, SQFP-48 |
| 文件頁數(shù)： | 15/46頁 |
| 文件大?。?/td> | 284K |
| 代理商： | LC89058W-E |
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LC89058W-E
No.A1056-22/64
10.1.6 PLL clock output
The PLL clock output is controlled by the PLLACC, PLLDV1, PLLDV2, or PRSEL[1:0].
PLLACC can be used to generate a PLL lock frequency for each S/PDIF input sampling frequency band.
Figure 10.3 PLL Clock Output Control
Table 10.2: PLL Clock Output Frequencies (Bold settings are recommended values.)
PLL Output
PLLACC=0 (Fixed multiple outputs of input fs)
PLLACC=1 (Fixed multiple outputs for each input fs band)
S/PDIF
fs
PRSEL=00
(256fs)
PRSEL=01
(512fs)
PRSEL=10
(128fs)
PLLDV0=0
PLLDV1=0
PLLDV0=1
PLLDV1=0
PLLDV0=0
PLLDV1=1
PLLDV0=1
PLLDV1=1
32kHz
8.19MHz
16.38MHz
4.09MHz
16.38MHz
8.19MHz
16.38MHz
8.19MHz
44.1kHz
11.28MHz
22.57MHz
5.64MHz
22.57MHz
11.28MHz
22.57MHz
11.28MHz
48kHz
12.28MHz
24.57MHz
6.14MHz
24.57MHz
12.28MHz
24.57MHz
12.28MHz
64kHz
16.38MHz
32.76MHz
8.19MHz
16.38MHz
16.38MHz
32.76MHz
88.2kHz
22.57MHz
45.15MHz
11.28MHz
22.57MHz
22.57MHz
45.15MHz
96kHz
24.57MHz
49.15MHz
12.28MHz
24.57MHz
24.57MHz
49.15MHz
128kHz
32.76MHz
65.53MHz
16.38MHz
16.38MHz
16.38MHz
176.4kHz
45.15MHz
90.31MHz
22.57MHz
22.57MHz
22.57MHz
192kHz
49.15MHz
98.30MHz
24.57MHz
24.57MHz
24.57MHz
If 128kHz, 176.4kHz or 192kHz input is received when the PLLACC is set to 0 and the PRSEL [1:0] to 01, the DC
characteristics of output directly sent to the RMCK pin cannot be guaranteed. In such a case, set the frequency to one
half or quarter of the PLL clock frequency (PRSEL [1:0]=00 or 10).
S/PDIF Input
512fs
Lock detection
Fs calculation
Fs=
32k, 44.1k, 48k
Fs=
64k, 88.2k, 96k
Fs=
128k, 176.4k, 192k
Yes
No
Yes
No
Yes
No
“PLLACC”
Lock
Unlock
PLL output
256fs
1
0
PLL fixation output
“PRSEL=00”: 256fs
“PRSEL=01”: 512fs
“PRSEL=10”: 128fs
PLL output
Free-run
PLL output
128fs
PLL output
512fs
PLL output
256fs
*
“PLLDV0”
PLL output
512fs
PLL output
256fs
“PLLDV1”
1
0
1
0
*: When the data is judged to exceed the value of
FSLIM [1:0] which limits the reception frequency of
the input S/PDIF, processing similar to PLL
unlocking is carried out and the processing does not
proceed to the subsequent step. The clock source is
automatically switched to the XIN source.
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