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參數(shù)資料
| 型號： | LC89058W-E |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, SQFP-48 |
| 文件頁數(shù)： | 19/46頁 |
| 文件大?。?/td> | 284K |
| 代理商： | LC89058W-E |
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LC89058W-E
No.A1056-26/64
10.1.10 Output clocks generated when input S/PDIF reception is limited
The same processing performed when the PLL is unlocked is carried out if an S/PDIF input exceeding the reception
range limit (which can be defined by FSLIM[1:0]) is supplied. The clock source is then switched to the XIN clock and
clocks are output from respective clock pins.
Figure 10.6 Output Clocks Generated When Input Data Reception Is Limited
DIN0-6
RMCK
RBCK
RLRCK
PLL status
fs=44.1kHz
fs=192kHz
LOCK
PLL clock
RERR
LOCK
PLL clock
DIN0-6
PLL status
fs=44.1kHz
fs=192kHz
LOCK
PLL clock
RERR
LOCK
XIN clock
fs=96kHz
LOCK
PLL clock
fs=96kHz
LOCK
PLL clock
DIN0-6
PLL status
fs=44.1kHz
fs=192kHz
LOCK
PLL clock
RERR
LOCK
XIN clock
fs=96kHz
LOCK
RMCK
RBCK
RLRCK
RMCK
RBCK
RLRCK
UNLOCK
XIN clock
(a) When set to FSLIM[1:0]=00 (No limit on inputs)
(b) When set to FSLIM[1:0]=01 (Receive frequency is limited to 96kHz or lower)
(c) When set to FSLIM[1:0]=10 (Receive frequency is limited to 48kHz or lower)
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