參數(shù)資料
型號(hào)： LC89058W-E
廠商： SANYO SEMICONDUCTOR CO LTD
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 MM, SQFP-48
文件頁(yè)數(shù)： 17/46頁(yè)
文件大?。?/td> 284K
代理商： LC89058W-E
LC89058W-E
No.A1056-24/64
10.1.8 Output clocks block diagram (RMCK, RBCK, RLRCK, SBCK, SLRCK, XMCK)
The relationships between the output clock and switch function are shown below.
PLL in the figure indicates the PLL source and XIN the XIN source.
The contents in the quotation marks “” by the switch function blocks correspond to the write command names.
The broken lines connecting the switches indicate coordinated switching.
Lock/Unlock is switched automatically by PLL locking/unlocking.
Figure 10.4 Clock Output Block Diagram
1/2
1/4
Mute
1/1
“PLLACC”
“XRSEL[1:0]”
Mute
12.288MH
6.144MHz
3.072MHz
64fs
PLL
“XRBCK[1:0]”
XIN
PLL
XIN
Mute
192kHz
96kHz
48kHz
fs
PLL
“XRLRCK[1:0]”
XIN
16fs
Mute
12.288MH
6.144MHz
3.072MHz
PLL
“XSBCK[1:0]”
“PSBCK[1:0]”
XIN
fs/4
Mute
192kHz
96kHz
48kHz
PLL
“XSLRCK[1:0]”
“PSLRCK[1:0]”
XIN
128fs
64fs
32fs
2fs
fs
fs/2
Mute
1/1
1/2
“XMSEL[1:0]”
“OCKSEL”
Lock / Unlock
Master
Clock
Generator
PLL Source
512fs
X’tal Source
12.288MHz
24.576MHz
SLRCK
RBCK
RMCK
XMCK
SBCK
RLRCK
512fs
1/2
1/4
512fs
256fs
128fs
Mute
1/1
12.288MHz
24.576MHz
Input fs
“PRSEL[1:0]”
“XINSEL”
Auto
“PLLDV1”
“RMCKP”
“SBCKP”
“SLRCKP”
“EXTSEL”
GPIO0
GPIO1
GPIO2
“EMCKP”
Master / Slave
“PLLDV0”
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