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參數(shù)資料
| 型號： | LC749450NW |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Silicon Gate CMOS IC Digital RGB Image Processor IC |
| 中文描述： | 硅柵CMOS集成電路數(shù)字RGB圖像處理器芯片 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 81K |
| 代理商： | LC749450NW |
No.8096-5/17
LC749450NW
Signal type
Video signals
Number of pins
10
10
10
1
Symbol
YIN
CBI
CRI
DHS
Description
Notes
Y or G
Cb or B or C
Cr or R or OSD
Horizontal sync signal
NTSC/PAL/DTV (4801, 480P, 1080I)
or progressive scan RGB (up to SXGA)
or NTSC/PAL decoder input
Pixel sync horizontal sync signal input
The polarity can be switched by setting the DVPOLIN internal register.
Vertical sync signal input
The polarity can be switched by setting the DVPOLIN internal register.
Valid video period enable signal (horizontal/composite)
Valid video period enable signal (vertical)
Field signal input
System clock input
System clock input
Fixed clock input or test clock input
System reset input, active low
—
Sync signals
1
DVS
Vertical sync signal
Data enable
signals
1
1
1
1
1
1
1
DEHI
DEVI
FIELD
CLKI
DCLKI
XTAL
XRST
—
Data enable
Vertical data enable
Field signal input
Clock
Used for the output dot clock
Pixel clock
Fixed oscillator
System reset
Total
System reset
—
40
I/O Specifications
Input Signals
Signal type
Video signals
Number of pins
10
10
10
1
Symbol
ODG
ODB
ODR
DHO
Description
Notes
G
B
R
Horizontal sync signal
RGB output
The LC749450NW also supports dithered 8-bit output.
Sync signals
This pin outputs the DHS pin input after a delay. (Used for pixel sync.)
(This can be set over the I
2
C bus.)
Outputs a vertical pixel sync signal.
Outputs a valid area signal.
1
1
DVO
AREA
Vertical sync signal
Data enable
Data enable
signals
Pixel clocks
Clamp pulse
signals
Clamp levels
1
1
CLKOUT
CLAMPO
Outputs the input clock
For A/D conversion
The polarity can be inverted.
Outputs a pulse signal used for A/D conversion clamp period verification
1
1
1
1
CLPG
CLPB
CLPR
ODEVPPO Field discrimination
Y/G clamp level
Cb/B clamp level
Cr/R clamp level
Clamp level discrimination output
(Too large: low, too small: high, match: high-impedance)
Field
discrimination
signals
Total
Outputs an odd/even field discrimination signal
(Used when IP conversion is not used.)
39
—
—
—
Output Signals
Signal type
I
2
C bus signals
Number of pins
1
1
1
Symbol
SDAIO
SCLI
SLADR
Description
Notes
Data bus
Bus clock
Slave switching
Used for setting internal registers and reading out the internal status.
The slave address is “1110000+(R/W)”.
Sets the I
2
C bus slave address.
Normally low, High: E2h, Low: E0h.
Data output enable signal
Data output
signals
XTAL
1
OE
1
XTALSW
This signal sets the XTAL clock pin input operation
High: The XTAL clock input signal is divided by 2.
—
Total
5
—
—
Control Signals
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