參數(shù)資料
型號(hào)： LC749450NW
廠商： Sanyo Electric Co.,Ltd.
英文描述： Silicon Gate CMOS IC Digital RGB Image Processor IC
中文描述： 硅柵CMOS集成電路數(shù)字RGB圖像處理器芯片
文件頁數(shù)： 10/17頁
文件大小： 81K
代理商： LC749450NW
No.8096-10/17
LC749450NW
Pin No.
Symbol
I/O circuit type
I/O
Circuit type
B
B
PHBT08
B
P
P
B
B
B
PHBT08
B
B
I
I
I
I
O
PHOT08
O
PHOT12
I
P
P
—
—
B
PHBT12
I
I
I
I
O
PHOT08
O
PHOT08
I
I
P
P
O
PHOT08
O
PHOT08
O
PHOT08
O
PHOT08
O
PHOT08
O
PHOT08
O
PHOT12
O
PHOT12
O
PHOT12
O
PHOT12
P
P
O
O
O
O
O
PHOT08
O
O
O
O
O
P
P
P
P
Connected to
Notes
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
GP_IO0
GP_IO1
GP_IO2
DV
DD
18
DV
SS
18
GP_IO3
GP_IO4
GP_IO5
GP_IO6
GP_IO7
GP_CS
GP_WR
GP_MOD
CPU_TST_SW
ODEVFFO
TSTO0
OE
DVD
DD
33
DV
SS
33
NC
NC
SDAIO
SCLI
SLADR
TST15
XTALSW
TSTO1
AREAO
DEVI
FIELD
DV
DD
18
DV
SS
18
TSTO2
DVO
DHO
TSTO3
TSTO4
CLAMPOO
CLPR
CLPG
CLPB
CLKOUT
DV
DD
33
DV
SS
33
ODR0
ODR1
ODR2
ODR3
ODR4
ODR5
ODR6
ODR7
ODR8
ODR9
DV
DD
18
DV
SS
18
DV
DD
33
DV
SS
33
CPU I/O or
Test circuit outputs
—
—
Power supply
GND
1.8 V system power supply
1.8 V system ground
CPU I/O or
Test circuit outputs
PHICD
PHICD
PHICD
PHISD
CPU bus chip enable input
CPU bus write enable input
CPU bus mode switch
CPU/test mode switch
Field discrimination signal output
Test output. This pin is normally left open.
Output enable
3.3 V system power supply
3.3 V system ground
No connection
No connection
I
2
C bus data I/O
I
2
C bus clock input
I
2
C bus slave address setting
Test input. This pin is normally left open.
XTAL clock pin input mode setting input
Test output. This pin is normally left open.
Valid area signal output
Vertical valid video period enable signal input
Field signal input
1.8 V system power supply
1.8 V system ground
Test output. This pin is normally left open.
Vertical sync signal output (The polarity can be switched.)
Horizontal sync signal output (The polarity can be switched.)
Test output. This pin is normally left open.
Test output. This pin is normally left open.
A/D conversion clamp period verification pulse output
Clamp control output (R/Cr)
Clamp control output (G/Y)
Clamp control output (B/Cb)
Clock output
3.3 V system power supply
3.3 V system ground
Open
PHISD
—
—
—
—
Power supply
GND
Open
Open
PHISD
PHISD
PHISD
PHISD
Open
Open
PHICD
PHICD
—
—
Power supply
GND
Open
Open
Open
—
—
Power supply
GND
R signal outputs
—
—
—
—
Power supply
GND
Power supply
GND
1.8 V system power supply
1.8 V system ground
3.3 V system power supply
3.3 V system ground
Continued from preceding page.
Continued on next page.
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