參數(shù)資料
型號(hào)： LC72710LW
廠商： Sanyo Electric Co.,Ltd.
英文描述： Mobile FM Multiplex Broadcast (DARC) Receiver IC with On-Chip VICS Decoder(移動(dòng)FM多路廣播接收器芯片帶片上VICS譯碼器)
中文描述： 移動(dòng)調(diào)頻多路廣播（DARC）接收器集成電路片VICS解碼器（移動(dòng)調(diào)頻多路廣播接收器芯片帶片上VICS譯碼器）
文件頁(yè)數(shù)： 23/33頁(yè)
文件大?。?/td> 168K
代理商： LC72710LW
Notes on Data Output Timing (Relationship with the received data)
Figure 3 shows the timing relationship between the received data and the interrupt control signal (INT). However, the
delay from the actual received signal due to demodulation operations in MSK demodulation blocks is ignored.
Block synchronization is established by discriminating the BIC code. As shown in figure 3, the data for the nth packet
can be output during reception of the following packet (number n+1).
Figure 4 shows the output timing for post-vertical correction data. In vertical correction, the data for a single frame is
stored in memory and the correction operation is performed if frame synchronization was established and it was not
possible to correct all the packet data in horizontal correction. The timing with which vertical correction is started is the
start of the frame. Horizontal correction is performed for each packet while packets 1 through 28 in the nth frame are
being received, and this data is passed to the CPU interface. Vertical correction is performed for the data from the
previous frame (frame n-1) in the unused time periods during that processing.
The vertical correction data consists of 190 blocks that are output, and this data is output at the rate of one block for
every block received, in order starting at the time the 29th packet (block) is received. Only data from the data blocks in
the FM multiplex broadcast frame structure is output, and the last block (block 190) is output during reception of the
218th block.
As indicated previously (page 21) packet data that was, for example, corrected completely by horizontal correction, is not
output in the vertical correction output data. (The INT signal is not issued.) However, the order in which the horizontal
output is produced is not speeded up by the amount of the packet data that is not output. For example, if data packets 1 to
100 were corrected by horizontal correction, output of the post-vertical correction packet data for packet 101 will not
occur at the reception position of block number 29 in figure 4, but at the reception position for packet data number 129.
No. 6166-23/33
LC72710W, 72710LW
BIC
BIC
18 ms
300 ns max
300 ns max
Packet n-1
Packet n+1
Packet n data
1 ms
Received
data
BCK
INT
Data cannot
be guaranteed
Packet n data output
Output period for
packet n+1 data
62.5
μ
s
68
μ
s
Figure 3 Received Data, Block Synchronization, and Data Output Timing
First
frame
BCK
FCK
INT
Output periods for
post-vertical correction
data from the previous
frame.
62.5
μ
s
Received block
signal
nth frame
18 ms
×
28 = 504 ms
189
190
2
1
271
272
1
2
3
28
29
30
31
220
219
218
18 ms
1 ms
18 ms
9 ms
9 ms
Figure 4 Post-Vertical Correction Data Output Timing
相關(guān)PDF資料
PDF描述
LC72711LW Mobile FM Multiplex Broadcast (DARC) Receiver IC(移動(dòng)FM多路廣播接收器芯片)
LC72714 Mobile FM Multiplex Broadcast IC with On-Chip VICS Decoder
LC72714W Mobile FM Multiplex Broadcast IC with On-Chip VICS Decoder
LC72720NM Single-Chip RDS Signal-Processing System LSI(單片無(wú)線電數(shù)據(jù)系統(tǒng)信號(hào)處理LSI（大規(guī)模集成電路）)
LC72720YV Single-Chip RDS Signal-Processing System IC(單片無(wú)線電數(shù)據(jù)系統(tǒng)信號(hào)處理芯片)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LC72710W 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Mobile FM Multiplex Broadcast DARC Receiver IC with On-Chip VICS Decoder
LC72711LW 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Mobile FM Multiplex Broadcast DARC Receiver IC
LC72711LW-E 制造商:ON Semiconductor 功能描述:DARC DECODE-LSI - Trays
LC72711LWHS-E 功能描述:射頻接收器 RoHS:否 制造商:Skyworks Solutions, Inc. 類型:GPS Receiver 封裝 / 箱體:QFN-24 工作頻率:4.092 MHz 工作電源電壓:3.3 V 封裝:Reel
LC72711W 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Mobile FM Multiplex Broadcast DARC Receiver IC
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