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參數(shù)資料
| 型號： | LC72710LW |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Mobile FM Multiplex Broadcast (DARC) Receiver IC with On-Chip VICS Decoder(移動FM多路廣播接收器芯片帶片上VICS譯碼器) |
| 中文描述： | 移動調(diào)頻多路廣播（DARC）接收器集成電路片VICS解碼器（移動調(diào)頻多路廣播接收器芯片帶片上VICS譯碼器） |
| 文件頁數(shù)： | 15/33頁 |
| 文件大小： | 168K |
| 代理商： | LC72710LW |
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No. 6166-15/33
LC72710W, 72710LW
Indicates the block number or the parity block number of the output data.
A single frame consists of data blocks numbered 0 to 189 and parity blocks numbered 0 to 81. Output following vertical
correction does not include parity block data.
The value of the block number register is undefined if VEC_HALT (bit 2 in control register 1) is set to 1.
Data Update Timing for Read Registers
The data in the two read registers (the status register at address 01H and the block number register at address 02H) is
updated in the 1 ms interval between 1 ms prior to the output of the interrupt control signal (INT) and a point
immediately before the INT output.
In normal processing, when an interrupt occurs, the application will first determine the nature of the data packet that will
be output by the current interrupt signal by reading out the status register, and determine if it is necessary to read out that
data. For example, if error correction failed and the erroneous data is not required, the application should simply wait for
the next interrupt.
If the CCB interface is used, the application reads out the data from CCB address #FB, and determines the status from the
additional 16 bits of data. It then either reads out the following data or sets the CE signal low to cancel the readout.
Applications can also read out data asynchronously with respect to the interrupt signal. In this case, the application
checks the current reception status by reading out the status register and checking bit 6 (data received in the block
synchronized state) and bit 5 (data received in the frame synchronized state). In this case, using data for which bit 7 (VH)
is 0 provides superior real time characteristics.
Block Number Register
CPU Interface Timing <Parallel Mode>
Register Read Timing
Address
Register
R/W
Initial value
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
02H
BLNO
R
—
BLN7
BLN6
BLN5
BLN4
BLN3
BLN2
BLN1
BLN0
t
CYRD
t
WRDL1
, t
WRDL2
A0 to A3
CS
t
HARD
t
SARD
t
DRDY
t
RDH
t
WRDY
Valid
output
RD
RDY
DATn
*
t
HARD
stipulates the earliest timing for A0 to A3 and CS.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC72710W | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Mobile FM Multiplex Broadcast DARC Receiver IC with On-Chip VICS Decoder |
| LC72711LW | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Mobile FM Multiplex Broadcast DARC Receiver IC |
| LC72711LW-E | 制造商:ON Semiconductor 功能描述:DARC DECODE-LSI - Trays |
| LC72711LWHS-E | 功能描述:射頻接收器 RoHS:否 制造商:Skyworks Solutions, Inc. 類型:GPS Receiver 封裝 / 箱體:QFN-24 工作頻率:4.092 MHz 工作電源電壓:3.3 V 封裝:Reel |
| LC72711W | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Mobile FM Multiplex Broadcast DARC Receiver IC |
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