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參數(shù)資料
| 型號： | LC72151V |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO30 |
| 封裝： | SSOP-30 |
| 文件頁數(shù)： | 28/29頁 |
| 文件大?。?/td> | 326K |
| 代理商： | LC72151V |
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No. 6976-8/29
LC72151V
Continued from preceding page.
Pin No.
Symbol
Usage
Function
Pin circuit
Dedicated output pin
Latches OUT3 in the control data and outputs data from O-3 pin.
This pin goes open state at a power-on reset.
5
O-3
Output port
Op-amp for PLL active low-pass filter
AVSS is the analog system ground pin shared with low-pass filter Nch
MOS transistor.
Voltage applied to AREF pin must be 1/2 that to VDD pin.
Note: Power must be applied to AVDD before applied to VDD, and AVDD
must be higher than or equal to VDD.
19
12
13
14
15
AIN1
AREF
AVDD
AVSS
AOUT1
Op-amp for low-pass filter amp
AREF
AIN1
+
–
AOUT1
AVSS
AVDD
PLL active low-pass filter Nch MOS transistor
Source of the transistor is connected to AVSS pin.
Note: Connect AVSS pin to ground in use.
24
25
AIN2
AOUT2
Transistor for low-pass
filter amp
AVSS
PLL charge pump output
When the frequency created by dividing the local oscillator signal
frequency by N is higher than the reference frequency, a high level is
output from the PD pin. When lower, a low level is output. The PD pin
goes to the high-impedance state when the frequencies match.
21
23
20
PDM1
PDM2
PDS
Charge pump output
PLL high-speed locking charge pump output
When the high-speed locking mode is selected, signal pulses is
output according to the frequency variation. This pin enters high-
impedance state when the local oscillation frequency enters the set
frequency range.
22
PDF
PLL high-speed locking charge
pump output
PLL high-speed locking active low-pass filter transmission gate
input/output dual function pins
Note: Connect AVSS pin to ground in use.
18
17
16
TGI1
TGI2
TGO
PLL high-speed locking TG
TGO
TGI2
TGI1
HCTR is selected by setting CTS1 in the control data to 1.
Input frequency: 0.4 to 25 MHz
The signal is input to a divide-by-2 circuit and the result is input to a
general-purpose counter. This counter can also be used as an
integrating counter.
The counter value is output as the result of the count, MSB first, from
the DO pin.
There are four measurement periods: 4, 8, 32, and 64 ms.
When H/I-3 in the control data is set, this pin functions as an input
port, and the value is output from the output pin DO.
10
HCTR/I-3
General-purpose counter
LCTR is selected by setting CTS1 in the control data to 1.
When the LCTR is selected as described above and CTS0 is set to 1:
This pin enters the frequency measurement mode.
Input frequency: 10 to 500 kHz
The signal is directly transmitted to the general-purpose counter.
When CTS0 is set to 0
This pin enters period measurement mode.
Input frequency: 1 Hz to 20 kHz
Period can be measured either in single period or in double period. If
double period measurement is selected, the frequency is 2 Hz to
40 kHz.
The counter value is output as the result of the count, MSB first, from
the DO pin.
When L/I-4 in the control data is set:
This pin functions as an input port, the value is output from the output
pin DO.
11
LCTR/I-4
General-purpose counter
Continued on next page.
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相關(guān)代理商/技術(shù)參數(shù) |
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| LC7216M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning |
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