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參數(shù)資料
| 型號： | LC72151V |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO30 |
| 封裝： | SSOP-30 |
| 文件頁數(shù)： | 15/29頁 |
| 文件大小： | 326K |
| 代理商： | LC72151V |
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General-purpose counter structure
No. 6976-22/29
LC72151V
4–7
8–11
12–15 16–19
0–3
S1
S2
S3
CTS0
CTS1
(T)
(FIF)
GT
GT1,GT0
M
S
B
L
S
B
CT
C = FIF
× GT
C = (1/T)
÷ 900kHz
E
HCTR
Single period/
double period
extraction circuit
LCTR
1
2
4/8/32/64
ms
DO pin
General-purpose counter
(20-bit binary counter)
I/O signal
switching gate
Check signal
Parameter
LCTR period measurement mode check signal frequency
X’tal OSC
10.25 MHz
10.35 MHz
fref = 30, 9, 3 kHz
fref = other than 30, 9, 3 kHz
Check signal
1025 kHz
1030 kHz
1150 kHz
CTS1
CTS0
Input pin
Measurement mode
Frequency range
Input sensitivity
S1
1
*
HCTR
Frequency
0.4 to 25.0 MHz
40 mVrms *1
S2
0
1
LCTR
Frequency
10 to 500 kHz
40 mVrms *1
S3
0
LCTR
Period
1.0 to 20
× 103 Hz
(Pulse)
*1: CTC = 0: 40 mVrms
CTC = 1: 70 mVrms
—: No stipulation ( Not guaranteed)
( ): Actual value (Reference value)
HCTR: Minimum input sensitivity regulation
f [MHz]
CTC
0.4
≤ f < 8
8
≤ f < 12
12
≤ f ≤ 25
0 (Normal mode)
40 mVrms
(5 to 15 mVrms)
1 (Degrade mode)
—
70 mVrms
—
(40 to 60 mVrms)
LCTR: Minimum input sensitivity regulation
f [MHz]
CTC
10
≤ f< 400
400
≤ f ≤ 500
0 (Normal mode)
40 mVrms
20 mVrms
(1 to 10 mVrms)
1 (Degrade mode)
—
70 mVrms
(15 to 30 mVrms)
GT1
GT0
Frequency measurement mode
Period measurement mode
Measurement time
Wait time
0
4 ms
3 to 4 ms
1 period
0
1
8
1
0
32
7 to 8 ms
2 periods
1
64
CTC: Input sensitivity select data. Input sensitivity is degraded by setting CTC to 1.
However, the actual value for HCTR is in the range 40 to 60 mVrms at 10.7 MHz, for LCTR is in the range 15 to
30 mVrms at 450 kHz.
CTP: Input pull-down can be inhibited by setting CTP to 1.
Set CTP to 1 4 ms before setting CTE to 1. Set CTP to 0 when the counter is not used.
Wait time will be reduced to 1 to 2 ms by setting CTP to 1.
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