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參數(shù)資料
| 型號： | LC72151V |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO30 |
| 封裝： | SSOP-30 |
| 文件頁數(shù)： | 14/29頁 |
| 文件大?。?/td> | 326K |
| 代理商： | LC72151V |
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Charge Pump Structure
Note: If the unlock state is detected when the channel changes, the sub-charge pump (PDS) operates. Since the sub-
charge pump operates concurrently with the main-charge pump, decrease the time constants for the low-pass filter
to accelerate the locking.
However, note that when the FMIN (high-speed mode) is selected and when the channel changes (during high-
speed locking control), both the main- and the sub-charge pumps do not operate and enter the high impedance
state, and forcibly implement an unlock judgement. When locked at a high-speed locking control completion, the
output is not extended but locking is instantaneously judged. By selecting sub-charge operation (during unlocked)
with FMIN (high-speed mode) selected, the sub-charge pump is forcibly operated to shorten the locking time for
the time set by the high-speed locking completion flag output wait time control data (HSE0, HSE1) after switching
from high-speed locking control to normal PLL operation.
No. 6976-21/29
LC72151V
PDM1
(MAIN)
PDM2
fvco/N
Phase
Detector
Unlock
Detector
and
Subcharge
Pump Cont
fref
Clock
Unlock
DZ0
UL0
UL1
PDC0
PDC1
DO
DLC
DZ1
(SUB)
PDS
PD
New high-speed
locking charge pump
Main-charge pump
Conventional high-speed
locking sub-charge pump
F
(High Speed)
Fast Lock Up
Control
TLR0,TLR1
CWS0,CWS1
HSE0,HSE1
PDC1
PDC0
PDS(Sub-charge pump state)
0
*
High impedance
1
Charge pump operating (at all times)
1
0
Charge pump operating (when PLL unlocked)
DLC
PDM1, PDM2, PDS
0
Normal operation
1
Forced low
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