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參數(shù)資料
| 型號： | LC66358B |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Four-bit Single-Chip Microcontrollers On-Chip 8 K-byte ROM(4位單片微控制器(帶8K字節(jié)片上ROM)) |
| 中文描述： | 四位單芯片微控制器片8的K -字節(jié)的光盤（4位單片微控制器（帶8K的字節(jié)片上光盤）） |
| 文件頁數(shù)： | 21/23頁 |
| 文件大?。?/td> | 267K |
| 代理商： | LC66358B |
Continued from preceding page.
Note: 9. Internal control registers can also be tested by executing this instruction immediately after a BANK instruction. However, this is limited to registers
that can be read out.
No. 4677-21/23
LC66354B, 66356B, 66358B
Continued on next page.
Mnemonic
Instruction code
Operation
Description
Affected
status bits
Note
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
PC7 to 0
←
P
7
P
6
P
5
Branch to the location in the
P
4
P
3
P
2
same page specified by P
0
to
P
1
P
0
P
7
if the bit in port (DP
L
)
if [P
specified by the immediate
(DP
L
), t2]
data t
1
t
0
is one.
= 1
PC7 to 0
←
P
7
P
6
P
5
Branch to the location in the
P
4
P
3
P
2
same page specified by P
0
to
P
1
P
0
P
7
if the bit in port (DP
L
)
if [P
specified by the immediate
(DP
L
), t2]
data t
1
t
0
is zero.
= 0
PC7 to 0
←
P
7
P
6
P
5
P
4
P
3
P
2
Branch to the location in the
P
1
P
0
same page specified by P
0
to
if (CF)
P
7
if CF is one.
= 1
PC7 to 0
←
P
7
P
6
P
5
P
4
P
3
P
2
Branch to the location in the
P
1
P
0
same page specified by P
0
to
if (CF)
P
7
if CF is zero.
= 0
PC7 to 0
←
P
7
P
6
P
5
P
4
P
3
P
2
Branch to the location in the
P
1
P
0
same page specified by P
0
to
if (ZF)
P
7
if ZF is one.
= 1
PC7 to 0
←
P
7
P
6
P
5
P
4
P
3
P
2
Branch to the location in the
P
1
P
0
same page specified by P
0
to
if (ZF)
P
7
if ZF is zero.
= 0
PC7 to 0
←
P
7
P
6
P
5
Branch to the location in the
P
4
P
3
P
2
same page specified by P
0
to
P
1
P
0
P
7
if the flag (of the 16 user
if (Fn)
flags) specified by n
3
n
2
n
1
n
0
= 1
is one.
PC7 to 0
←
P
7
P
6
P
5
Branch to the location in the
P
4
P
3
P
2
same page specified by P
0
to
P
1
P
0
P
7
if the flag (of the 16 user
if (Fn)
flags) specified by n
3
n
2
n
1
= 0
n
0
is zero.
Input the contents of port 0
to AC.
BPt2 addr
Branch on port bit
1
1
0
1
1
0
t
1
t
0
2
2
9
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
BNPt2
addr
Branch on no port
bit
1
0
0
1
1
0
t
1
t
0
2
2
9
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
1
1
0
1
1
1
0
0
BC addr
Branch on CF
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
2
2
1
0
0
1
1
1
0
0
BNC addr
Branch on no CF
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
2
2
1
1
0
1
1
1
0
1
BZ addr
Branch on ZF
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
2
2
1
0
0
1
1
1
0
1
BNZ addr
Branch on no ZF
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
2
2
1
1
1
1
n
3
n
2
n
1
n
0
P
3
P
2
P
1
P
0
BFn4 addr Branch on flag bit
P
7
P
6
P
5
P
4
2
2
BNFn4
addr
Branch on no flag
bit
1
0
1
1
n
3
n
2
n
1
n
0
P
3
P
2
P
1
P
0
P
7
P
6
P
5
P
4
2
2
IP0
Input port 0 to AC
0
0
1
0
0
0
0
0
1
1
AC
←
(P0)
ZF
IP
Input port to AC
0
0
1
0
0
1
1
0
1
1
AC
←
[P (DP
L
)]
Input the contents of port
P (DP
L
) to AC.
Input the contents of port
P (DP
L
) to M (HL).
Input the contents of P (i4)
to AC.
ZF
IPM
Input port to M
0
0
0
1
1
0
0
1
1
1
M (HL)
←
[P (DP
L
)]
IPDR i4
Input port to AC
direct
1
0
1
1
0
1
0
0
1
I
3
1
I
2
1
I
1
1
I
0
2
2
AC
←
[P (i4)]
ZF
Input port 4, 5 to
E, AC respectively
1
1
1
1
0
0
0
1
1
0
1
1
1
0
1
0
E
←
[P (4)]
AC
←
[P (5)]
Input the contents of ports
P (4) and P (5) to E and AC
respectively.
IP45
2
2
OP
Output AC to port
0
0
1
0
0
1
0
1
1
1
P (DP
L
)
←
(AC)
Output the contents of AC to
port P (DP
L
).
Output the contents of M (HL)
to port P (DP
L
).
Output the contents of AC
to P (i4).
OPM
Output M to port
0
0
0
1
1
0
1
0
1
1
P (DP
L
)
←
[M (HL)]
OPDR i4
Output AC to port
direct
1
0
1
1
0
1
0
1
1
I
3
1
I
2
1
I
1
1
I
0
2
2
P (i4)
←
(AC)
Output E, AC to
port 4, 5
respectively
1
1
1
1
0
0
0
1
1
0
1
1
1
0
1
1
P (4)
←
(E)
P (5)
←
(AC)
Output the contents of E and
AC to ports P (4) and P (5)
respectively.
OP45
2
2
I
g
N
b
N
c
B
I
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