
LC6527N/F/L, LC6528N/F/L
No. 4363-39/43
2-1-3. Operation of sample application circuit – (1)
(a) At the time of power-ON reset
After power rises, a reset occurs automatically and the execution of the program starts at address 000H of the program
counter (PC).
– Note –
This sample application circuit provides an indeterminate region where no reset occurs before the operating V
DD
range
is entered.
(b) At the time of instantaneous break
(i)
When the P
XX
input voltage does not meet V
IL
(the P
XX
input level does not get lower than input threshold level
V
IL
) and the RES input voltage only meets V
IL
:
A reset occurs in the normal mode, providing the same operation as power-ON reset.
(ii) When both of the P
XX
input voltage and RES input voltage do not meet V
IL
:
The program continues running in the normal mode.
(iii) When both of the P
XX
input voltage and RES input voltage meet V
IL
:
When two pollings do not regard the P
XX
input voltage as "L" level, the HALT mode is not entered and reset
occurs.
When two pollings regard the P
XX
input voltage as "L" level, the HALT mode is entered and after power is
restored a reset occurs, releasing the standby mode.
(c) At the time of return from power failure backup
After power is restored, a reset occurs, releasing the standby mode.
2-1-4. Notes for design of sample application circuit – (1)
V
+
rise time and C2
Make the time constant (C2, R) of the reset circuit 10 times as long as the V
+
rise time. (R: ON-chip resistor,
200kohms typ.)
Make the V
+
rise time shorter (up to 20ms).
R1 and C1
Make the R1 value as small as possible. Make the C1 value as large as possible according to the backup time calcu-
lated. (Fix the R1 value so that the C1 charging current does not exceed the power source capacity.)
R2 and R3
Make the "H"-level input voltage applied to the P
XX
pin equal to V
DD
.
R4
Fix the time constant of C2 and C4 so that C2 can discharge during the period of time from when V
+
gets lower than
V
+
TRON (TR OFF) at the time of instantaneous break until the P
XX
input voltage gets lower than V
IL
(because release
by reset is not available after the HALT mode is entered by instantaneous break).
R5 and R6
Make V
+
(V
BE
= 0.6V is obtained by R5 and R6) when the reset circuit works (Tr ON) more than (operating V
DD
min
+ V
F
of diode D1).
Observing this note, make V
+
as low as possible to provide a reset early enough after power-ON.
Backup time
The normal operastion continues with a relatively high current dissipation from when power failure is detected by the
P
XX
until the HALT instruction is executed. Fix the C1 value so that the standby supply voltage is held during backup
time of set + above-mentioned time.
2-1-5. Notes for software design
Design the program so that port A
3
is brought to "H" level at the standby mode.
Check a standby request by polling the input port twice.
(Example)
BP1
BP1
HALT
AAA
AAA
; 1st polling
; 2nd polling
; Standby
AAA: