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LC6527N/F/L, LC6528N/F/L
No. 4363-31/43
Mnemonic
Instruction code
Function
Description
Status flag
affected
Remarks
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
CI data
Compare AC with
immediate data
0 0 1 0
0 1 0 0
1 1 0 0
I
3
I
2
I
1
I
0
2 2 I
3
I
2
I
1
I
0
+ (AC) + 1
ZF CF
LI data
Load AC with
immediate data
1 1 0 0
I
3
I
2
I
1
I
0
1 1 AC
←
I
3
I
2
I
1
I
0
ZF
*1
S
Store AC to M
0 0 0 0
0 0 1 0
1 1 M(DP)
←
(AC)
L
Load AC from M
0 0 1 0
0 0 0 1
1 1 AC
←
[M(DP)]
ZF
LDZ data Load DP
with Zero
and DP
L
with
immediate data
respectively
1 0 0 0
I
3
I
2
I
1
I
0
1 1 DP
H
←
0
DP
L
←
I
3
I
2
I
1
I
0
LHI data
Load DP
H
with
immediate data
0 1 0 0
0 0 I
1
I
0
1 1 DP
H
←
I
1
I
0
IND
Increment DP
L
1 1 1 0
1 1 1 0
1 1 DP
L
←
(DP
L
) + 1
ZF
DED
Decrement DP
L
1 1 1 0
1 1 1 1
1 1 DP
L
←
(DP
L
) – 1
ZF
TAL
Transfer AC to DP
L
1 1 1 1
0 1 1 1
1 1 DP
L
←
(AC)
TLA
Transfer DP
L
to AC
1 1 1 0
1 0 0 1
1 1 AC
←
(DP
L
)
ZF
JMP addr Jump
0 1 1 0
P
7
P
6
P
5
P
4
1 0 P
9
P
8
2 2 PC
←
P
9
P
8
P
7
P
6
P
5
P
3
P
2
P
1
P
0
P
4
P
3
P
2
P
1
P
0
CZP addr Call subroutine in the
zero page
1 0 1 1
P
3
P
2
P
1
P
0
1 1 STACK
←
(PC) + 1
PC
9—6
PC
1—0
←
0
PC
5—2
←
P
3
P
2
P
1
P
0
CAL addr Call subroutine
1 0 1 0
P
7
P
6
P
5
P
4
1 0 P
9
P
8
2 2 STACK
←
(PC) + 2
P
3
P
2
P
1
P
0
PC
9—0
←
P
6
5
P
4
P
3
P
2
P
1
P
0
RT
Return from
subroutine
0 1 1 0
0 0 1 0
1 1 PC
←
(STACK)
BA
t
addr
Branch on AC bit
0 1 1 1
P
7
P
6
P
5
P
4
0 0 t
1
t
0
2 2 PC
7—0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
P
3
P
2
P
1
P
0
if AC
t
= 1
BNA
t
addr
Branch on no AC bit
0 0 1 1
P
7
P
6
P
5
P
4
0 0 t
1
t
0
2 2 PC
7—0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
P
3
P
2
P
1
P
0
if AC
t
= 0
BM
t
addr Branch on M bit
0 1 1 1
P
7
P
6
P
5
P
4
0 1 t
1
t
0
2 2 PC
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
P
3
P
2
P
1
P
0
if [M(DP, t
1
t
0
)] = 1
The AC contents and the
immediate data I
I
I
I
are
compared and the ZF and CF
are set/reset.
Comparison result CF
ZF
I
3
I
2
I
1
I
0
> (AC)
0
0
I
3
I
2
I
1
I
0
= (AC)
1
1
I
3
I
2
I
1
I
0
< (AC)
1
0
The immediate data I
3
I
2
I
1
I
0
is
loaded in the AC.
The AC contents are stored in
the M(DP).
The M(DP) contents are loaded
in the AC.
The DP
and DP
are loaded
with 0 and the immediate data
I
3
I
2
I
1
I
0
respectively.
The DP
is loaded with the
immediate data I
1
I
0
.
The DP
contents are
incremented + 1.
The DP
contents are
decremented – 1.
The AC contents are
transferred to the DP
L
.
The DP
L
contents are
transferred to the AC.
A jump to the address specified
with immediate data
P
9
P
8
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
occurs.
A subroutine is page 0 is
called.
A subroutine is called.
A return from a subroutine
occurs.
If a single bit of the AC
specified with the immediate
data t
1
t
0
is 1, a branch to the
address specified with the
immediate data
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
within the
same page occurs.
If a single bit of the AC
specified with the immediate
data t
1
t
0
is 0, a branch to the
address specified with the
immediate data
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
within the
same page occurs.
If a single bit of the M(DP)
specified with the immediate
data t
t
is 1, a branch to the
address specified with the
immediate data
P
P
P
P
P
P
P
P
0
within the
same page occurs.
Mnemonic
is BA0 to
BA3
according to
the value of
t.
Mnemonic
is BNA0 to
BA3
according to
the value of
t.
Mnemonic
is BM0 to
BM3
according to
the value of
t.
B
C
I
g
L
i
D
J
B