參數(shù)資料
型號： LC6527F
廠商： Sanyo Electric Co.,Ltd.
英文描述： Single-chip 4-bit Microcomputer for Small-scale Control-oriented Applications(用于小規(guī)?？刂贫ㄎ粦?yīng)用的單片4位微控制器)
中文描述： 單芯片四小規(guī)模的控制位微機(jī)化應(yīng)用（用于小規(guī)模控制定位應(yīng)用的單片4位微控制器）
文件頁數(shù)： 32/43頁
文件大?。?/td> 1469K
代理商： LC6527F
LC6527N/F/L, LC6528N/F/L
No. 4363-32/43
Mnemonic
Instruction code
Function
Description
Status flag
affected
Remarks
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
BNM
t
addrBranch on no M bit
0 0 1 1
P
7
P
6
P
5
P
4
0 1 t
1
t
0
2 2 PC
7—0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
P
3
P
P
1
P
0
if [M(DP, t
1
t
0
)] = 0
BP
t
addr
Branch on Port bit
0 1 1 1
P
7
P
6
P
5
P
4
1 0 t
1
t
0
2 2 PC
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
P
3
P
2
P
1
P
0
if [P(DP
L
t
1
t
0
)] = 1
BNP
t
addr Branch on no Port bit
0 0 1 1
P
7
P
6
P
5
P
4
1 0 t
1
t
0
2 2 PC
7—0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
P
3
P
2
P
1
P
0
if [P(DP
L
, t
1
t
0
)] = 0
BTM addr Branch on timer
0 1 1 1
P
7
P
6
P
5
P
4
1 1 0 0
P
3
P
2
P
1
P
0
2 2 PC
7—0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if TMF = 1
then TMF
←
0
TMF
BNTM addr
Branch on no timer
0 0 1 1
P
7
P
6
P
5
P
4
1 1 0 0
P
3
P
2
P
1
P
0
2 2 PC
7—0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if TMF = 0
then TMF
←
0
TMF
BC addr
Branch on CF
0 1 1 1
P
7
P
6
P
5
P
4
1 1 1 1
P
3
P
2
P
1
P
0
2 2 PC
7–0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if CF = 1
BNC addr Branch on no CF
0 0 1 1
P
7
P
6
P
5
P
4
1 1 1 1
P
3
P
2
P
1
P
0
2 2 PC
7–0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if CF = 0
BZ addr
Branch on ZF
0 1 1 1
P
7
P
6
P
5
P
4
1 1 1 0
P
3
P
2
P
1
P
0
2 2 PC
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if ZF = 1
BNZ addr Branch on no ZF
0 0 1 1
P
7
P
6
P
5
P
4
1 1 1 0
P
3
P
2
P
1
P
0
2 2 PC
7–0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if ZF = 0
IP
Input port to AC
0 0 0 0
1 1 0 0
1 1 AC
←
[P(DP
L
)]
ZF
OP
Output AC to port
0 1 1 0
0 0 0 1
1 1 P(DP
L
)
←
(AC)
SPB bit
Set port bit
0 0 0 0
0 1 B
1
B
0
1 2 P(DP
L
, B
1
B
0
)
←
1
RPB bit
Reset port bit
0 0 1 0
0 1 B
1
B
0
1 2 P(DP
L
, B
1
B
0
)
←
0
ZF
If a single bit of the M(DP)
specified with the immediate
data t
1
t
0
is 0, a branch to the
address specified with the
immediate data
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
within the
same page occurs.
If a single bit of port P(DP
)
specified with the immediate
data t
1
t
0
is 1, a branch to the
address specified with the
immediate data
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
within the
same page occurs.
If a single bit of port P(DP
L
)
specified with the immediate
data t
t
is 0, a branch to the
address specified with the
immediate data
P
P
P
P
P
P
P
P
0
within the
same page occurs.
If the TMF is 1, a branch to the
address specified with the
immediate data
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
within the
same page occurs. The TMF is
reset.
If the TMF is 0, a branch to the
address specified with the
immediate data
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
within the
same page occurs. The TMF is
reset.
If the CF is 1, a branch to the
address specified with the
immediate data
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
within the
same page occurs.
If the CF is 0, a branch to the
address specified with the
immediate data
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
within the
same page occurs.
If the ZF is 1, a branch to the
address specified with the
immediate data
P
P
P
P
P
P
P
P
0
within the
same page occurs.
If the ZF is 0 a branch to the
addressd specified with the
immediate data
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
within the
same page occurs.
Port P(DP
L
) contents are
loaded in the AC.
The AC contents are outputted
to port P(DP
L
).
A single bit in prot P(DP
L
)
specified with the immediate
data B
1
B
0
is set.
A single bit in port P(DP
L
)
specified with the immediate
data B
1
B
0
is reset.
Mnemonic is
BNM0 to
BNM3
according to
the value of
t.
Mnemonic is
BP0 to BP3
according to
the value of
t.
Mnemonic is
BNP0 to
BNP3
according to
the value of
t.
When this
instruction is
executed,
the E
contents are
destroyed.
When this
instruction is
executed,
the E
contents are
destroyed.
B
C
I
g
I
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