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| 型號： | LC651202F |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 4-Bit Single-Chip Microcontrollers for Small-Scale Control Applications |
| 中文描述： | 4位單片微控制器的小型規(guī)?？刂浦械膽?yīng)用 |
| 文件頁數(shù)： | 35/35頁 |
| 文件大?。?/td> | 312K |
| 代理商： | LC651202F |
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This catalog provides information as of November, 1997. Specifications and information herein are subject to
change without notice.
I
No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
I
Anyone purchasing any products described or contained herein for an above-mentioned use shall:
Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
I
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
No. 5190-35/35
LC651204N/F/L, LC651202N/F/L
Instruction code
Modified
Mnemonic
Operation
Description
status
Notes
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
flags
BNTM addr
Branch on no timer
0
P
7
P
6
P
5
P
4
0
1
1
1
P
3
P
2
P
1
P
0
1
0
0
2
2
PC
7
to
0
←
P
7
P
6
P
5
P
4
P
7
P
6
P
5
P
4
if TMF = 0
then TMF
←
0
PC
7
to
0
←
P
7
P
6
P
5
P
4
P
7
P
6
P
5
P
4
if EXTF = 1
then EXTF
←
0
PC
7
to
0
←
P
7
P
6
P
5
P
4
P
7
P
6
P
5
P
4
if EXTF = 0
then EXTF
←
0
PC
7
to
0
←
P
7
P
6
P
5
P
4
P
7
P
6
P
5
P
4
if EXTF = 0
PC
7
to
0
←
P
7
P
6
P
5
P
4
P
7
P
6
P
5
P
4
if CF = 0
PC
7
to
0
←
P
7
P
6
P
5
P
4
P
7
P
6
P
5
P
4
if ZF = 1
PC
7
to
0
←
P
7
P
6
P
5
P
4
P
7
P
6
P
5
P
4
if ZF = 0
PC
7
to
0
←
P
7
P
6
P
5
P
4
P
7
P
6
P
5
P
4
if Fn = 1
Branches to the location on the
same page specified by P
to P
0
TMF
if TMF is 0. Also clears TMF.
BI addr
Branch on interrupt
0
P
7
P
6
P
5
P
4
1
1
1
1
P
3
P
2
P
1
P
0
1
0
1
2
2
Branches to the location on the
same page specified by P
to P
0
EXTF
if EXTF is 1. Also clears EXTF.
BNI addr
Branch on no interrupt
0
P
7
P
6
P
5
P
4
0
1
1
1
P
3
P
2
P
1
P
0
1
0
1
2
2
Branches to the location on the
same page specified by P
to P
0
EXTF
if EXTF is 0. Also clears EXTF.
BC addr
Branch on CF
0
P
7
P
6
P
5
P
4
1
1
1
1
P
3
P
2
P
1
P
0
1
1
1
2
2
Branches to the location on the
same page specified by P
7
to P
0
if CF is 1.
Branches to the location on the
same page specified by P
7
to P
0
if CF is 0.
Branches to the location on the
same page specified by P
7
to P
0
if ZF is 1.
Branches to the location on the
same page specified by P
7
to P
0
if ZF is 0.
Branches to the location on the
same page specified by P
to P
0
if the bit in the 16 flags specified
by n
3
n
2
n
1
n
0
is 1.
Branches to the location on the
same page specified by P
to P
0
if the bit in the 16 flags specified
by n
3
n
2
n
1
n
0
iis 0.
Inputs the contents of port
P(DP
L
) to AC.
Outputs the contents of AC to
port P(DP
L
).
Sets to 1 the bit in port P(DP
)
specified by the immediate data
B
1
B
0
.
BNC addr
Branch on no CF
0
P
7
P
6
P
5
P
4
0
1
1
1
P
3
P
2
P
1
P
0
1
1
1
2
2
BZ addr
Branch on ZF
0
P
7
P
6
P
5
P
4
1
1
1
1
P
3
P
2
P
1
P
0
1
1
0
2
2
BNZ addr
Branch on no ZF
0
P
7
P
6
P
5
P
4
0
1
1
1
P
3
P
2
P
1
P
0
1
1
0
2
2
BFn addr
Branch on flag bit
1
P
7
P
6
P
5
P
4
1
0
1
n
3
P
3
P
2
P
1
P
0
n
2
n
1
n
0
2
2
BNFn addr
Branch on no flag bit
1
P
7
P
6
P
5
P
4
0
0
1
n
3
P
3
P
2
P
1
P
0
n
2
n
1
n
0
2
2
PC
7
to
0
←
P
7
P
6
P
5
P
4
P
7
P
6
P
5
P
4
if Fn = 0
IP
Input port to AC
0
0
0
0
1
1
0
0
1
1
AC
←
[P(DP
L
)]
ZF
OP
Output port to AC
0
1
1
0
0
0
0
1
1
1
P(DP
L
, B1 B0)
←
(AC)
SPB bit
Set port bit
0
0
0
0
0
1
B
1
B
0
1
2
P(DP
L
, B1 B0)
←
1
RPB bit
Reset port bit
0
0
1
0
0
1
B
1
B
0
1
2
P(DP
L
, B1 B0)
←
1
Clears to 0 the bit in port
P(DP
) specified by the
immediate data B
1
B
0
.
ZF
SCTL bit
Set control register bit
(S)
0
0
1
0
1
1
0
0
2
2
CTL
←
(CTL)
∨
Sets the bit (or bits) in the
control register specified by B
3
B
2
B
1
B
0
.
Clears the bit (or bits) in the
control register specified by B
3
B
2
B
1
B
0
.
Loads the contents of E and AC TMF
Stops all operations.
B
3
B
2
B
1
B
0
RCTL bit
Reset control register bit
(S)
0
1
0
0
1
0
0
1
1
B
3
B
2
B
1
B
0
1
0
0
2
2
CTL
←
(CTL)
∨
B
3
B
2
B
1
B
0
ZF
WTTM
Write timer
1
1
1
1
1
0
1
1
1
1
TM
←
(E), (AC)
TMF
←
0
HALT
Halt
1
1
1
1
0
1
1
0
1
1
Halt
NOP
No operation
0
0
0
0
0
0
0
0
1
1
No operation
Consumes one machine cycle
while performing no operation.
I
B
I
O
N
The mnemonics are
BF0
to
reflecting theBF15,
of n.
The mnemonics are
BFN0 to BFN15,
reflecting the value
of n.
Executing
instruction destthis
the contents of the E
register.
Executing
instruction destthis
the contents of the E
register.
This instruction is
disabled only when
all bits in port PA are
0.
N
Continued from preceding page.
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