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| 型號： | LC651202F |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 4-Bit Single-Chip Microcontrollers for Small-Scale Control Applications |
| 中文描述： | 4位單片微控制器的小型規(guī)模控制中的應(yīng)用 |
| 文件頁數(shù)： | 34/35頁 |
| 文件大?。?/td> | 312K |
| 代理商： | LC651202F |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁
No. 5190-34/35
LC651204N/F/L, LC651202N/F/L
Instruction code
Modified
Mnemonic
Operation
Description
status
Notes
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
flags
Load DP
with Zero and
DP
with immediate data
respectively
Load DPH with immediate
data
Increment DP
L
Decrement DP
L
Transfer AC to DP
L
Transfer DPL to AC
DP
H
←
0
DP
L
←
I
3
I
2
I
1
I
0
Loads 0 into DP
and the
immediate data I3I2I1I0 into DP
L
.
LDZ data
1
0
0
0
I
3
I
2
I
1
I
0
1
1
LHI data
0
1
0
0
I
3
I
2
I
1
I
0
1
1
DP
H
←
I
3
I
2
I
1
I
0
Loads the immediate data
I
3
I
2
I
1
I
0
into DP
H
.
Increments the contents of DP
L
. ZF
Decrements the contents of DP
L
. ZF
Moves the contents of AC to DP
L
.
Moves the contents of DPL to AC.
ZF
Exchanges the contents of AC
and DP
H
.
Exchanges the contents of AC
and the working register A0, A1,
A2, or A3 specified by t1t0.
IND
DED
TAL
TLA
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
1
0
1
1
1
1
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
DP
L
←
(DP
L
) + 1
DP
L
←
(DP
L
) – 1
DP
L
←
(AC)
AC
←
(DP
L
)
XAH
Exchange AC with DPH
0
0
1
0
0
0
1
1
1
1
(AC)
(DP
H
)
XAt
XA0
XA1
XA2
XA3
XHa
XH0
XH1
XLa
XL0
XL1
t1
0
0
1
1
t0
0
1
0
1
a
0
1
a
0
1
Exchange AC with working
register At
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
(AC)
(A0)
(AC)
(A1)
(AC)
(A2)
(AC)
(A3)
Exchange DPH with working
register Ha
Exchanges the contents of DP
H
and the working register H0 or H1
specified by a.
Exchanges the contents of DP
L
and the working register L0 or L1
specified by a.
Sets the flag specified by B
3
B
2
B
1
B
0
to 1.
Clears the flag specified by B
3
B
2
B
1
B
0
to 0.
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
(DP
H
)
(H0)
(DP
H
)
(H1)
Exchange DPH with working
register Ha
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
(DP
L
)
(L0)
(DP
L
)
(L1)
SFB flag
Set flag bit
0
1
0
1
B
3
B
2
B
1
B
0
1
1
Fn
←
1
RFB flag
Reset flag bit
0
0
0
1
B
3
B
2
B
1
B
0
1
1
Fn
←
0
ZF
0
P
7
P
6
P
5
P
4
1
1
0
1
P
3
P
2
P
1
P
0
P
10
P
9
P
8
PC
←
P
10
P
9
P
8
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
by the immediate data P
10
P
9
P
8
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
.
Jumps to the location given by
replacing the lower 8 bits of the
PC with E and AC.
STACK
←
(PC) + 1
PC
10
to
6
, PC
1
to
0
←
0
Calls a subroutine on page 0.
PC
5
to
2
←
P
3
P
2
P
1
P
0
STACK
←
(PC) + 2
Calls a subroutine.
PC
←
(STACK)
Returns from a subroutine.
PC
←
(STACK)
Returns from an interrupt
CF, ZF
←
CSF, ZSF
handling routine.
Specifies a pseudo I/O port
and changes the bank.
Jumps to the location specified
JMP addr
Jumping in the current bank
2
2
JPEA
Jumping current page
modified by E and AC
1
1
1
1
1
0
1
0
1
1
PC
0
to
7
←
(E, AC)
CZP addr
Call subroutine in the zero
page
1
0
1
1
P
3
P
2
P
1
P
0
1
1
CAL addr
RT
Call subroutine
Return from subroutine
1
0
0
1
1
1
0
0
1
0
P
10
P
9
P
8
0
1
2
1
2
1
0
RTI
Return from interrupt routine
0
0
1
0
0
0
1
0
1
1
ZF CF
BANK
Change bank
1
1
1
1
1
1
0
1
1
1
BAt addr
Change bank
0
P
7
P
6
P
5
P
4
1
1
1
0
P
3
P
2
P
1
P
0
0
t
1
t
0
2
2
PC
7
to
0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if ACt = 1
Branches to the location on the
same page specified by P
to P
0
if the bit in AC specified by the
immediate data t1t0 is 1.
Branches to the location on the
same page specified by P
to P
0
if the bit in AC specified by the
immediate data t1t0 is 0.
Branches to the location on the
same page specified by P
to P
0
if the bit in M(DP) specified by
the immediate data t
1
t
0
is 1.
Branches to the location on the
same page specified by P
to P
0
if the bit in M(DP) specified by
the immediate data t
1
t
0
is 0.
Branches to the location on the
same page specified by P
to P
0
if the bit in port P(DPL) specified
by the immediate data t
1
t
0
is 1.
Branches to the location on the
same page specified by P
to P
0
if the bit in port P(DPL) specified
by the immediate data t
1
t
0
is 0.
Branches to the location on the
same page specified by P
to P
0
TMF
if TMF is 1. Also clears TMF.
BNAt addr
Branch on no AC bit
0
P
7
P
6
P
5
P
4
0
1
1
0
P
3
P
2
P
1
P
0
0
t
1
t
0
2
2
PC
7
to
0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if ACt = 0
BMt addr
Branch on M bit
0
P
7
P
6
P
5
P
4
1
1
1
0
P
3
P
2
P
1
P
0
1
t
1
t
0
2
2
PC
7
to
0
←
P
7
P
6
P
5
P
4
P
3
P
P
1
P
0
if [M(DP, t
1
t
0
)] = 1
BNMt addr
Branch on no M bit
0
P
7
P
6
P
5
P
4
0
1
1
0
P
3
P
2
P
1
P
0
1
t
1
t
0
2
2
PC
7
to
0
←
P
7
P
6
P
5
P
4
P
3
P
P
1
P
0
if [M(DP, t
1
t
0
)] = 0
BPt addr
Branch on Port bit
0
P
7
P
6
P
5
P
4
1
1
1
1
P
3
P
2
P
1
P
0
0
t
1
t
0
2
2
PC
7
to
0
←
P
7
P
6
P
5
P
4
P
3
P
P
1
P
0
if [P(DP
L
, t
1
t
0
)] = 1
BNPt addr
Branch on no Port bit
0
P
7
P
6
P
5
P
4
0
1
1
1
P
3
P
2
P
1
P
0
0
t
1
t
0
2
2
PC
7
to
0
←
P
7
P
6
P
5
P
4
P
3
P
P
1
P
0
if [P(DP
L
, t
1
t
0
)] = 0
0
P
7
P
6
P
5
P
4
1
1
1
1
P
3
P
2
P
1
P
0
0
0
0
PC
7
to
0
←
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
if TMF = 0
then TMF
←
0
BTM addr
Branch on timer
2
2
I
D
W
M
i
J
B
N
The flags are divided
into four groups, F0
to F3, F4 to F7, F8 to
F11, and F12 to F15.
ZF is set or cleared
according to the 4
bits included in the
specified flags.
Only valid for the
i m m e d i a t e l y
following JMP, I/O,
or branch instruction.
The mnemonics are
BA0
to
reflecting the BA3,
of t.
The mnemonics are
BNA0 to BNA3,
reflecting the value
of t.
The mnemonics are
BM0
to
reflecting the BM3,
of t.
The mnemonics are
BNM0 to BNM3,
reflecting the value
of t.
The mnemonics are
BP0
to
reflecting the BP3,
of t.
The mnemonics are
BNP0 to BNP3,
reflecting the value
of t.
N
Continued from preceding page.
Continued on next page.
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