參數(shù)資料
型號: LC651202F
廠商: Sanyo Electric Co.,Ltd.
英文描述: 4-Bit Single-Chip Microcontrollers for Small-Scale Control Applications
中文描述: 4位單片微控制器的小型規(guī)??刂浦械膽?yīng)用
文件頁數(shù): 15/35頁
文件大?。?/td> 312K
代理商: LC651202F
No. 5190-15/35
LC651204N/F/L, LC651202N/F/L
Parameter
Symbol
Conditions
Applicable pins/notes
Ratings
V
DD
(v)
min
typ
max
Unit
Serial input
Data setup time
t
ICK
Stipulated with respect to the rising edge
of SCK.
SI
0.4
μs
Data hold time
t
CKI
Figure 5
SI
0.4
μs
Serial output
Stipulated with respect to the falling edge
of SCK.
For n-channel open-drain outputs only:
External resistance: 1 k
, external
capacitance: 50 pF
Figure 5
Output delay time
t
CKO
SO
0.6
μs
Pulse output
Period
High-level pulse width
t
PCY
Figure 6
Tcyc = 4 x the system clock period
For n-channel open-drain outputs only:
External resistance: 1 k
, external
capacitance: 50 pF
PE0
64
×
T
CYC
μs
t
PH
PE0
32
×
T
CYC
±10%
32
×
T
CYC
±10%
μs
Low-level pulse width
t
PL
PE0
μs
C
W
When PE1 has open-drain output
specifications
WDR
0.1±5%
μF
Guaranteed
constants
*
7
R
W
When PE1 has open-drain output
specifications
WDR
680±1%
k
3 to 5.5
R
l
When PE1 has open-drain output
specifications
WDR
100±1%
Clear time (discharge) t
WCT
Clear period (charge) t
WCCY
See Figure 7.
WDR
100
μs
See Figure 7.
WDR
29
ms
C
W
When PE1 has open-drain output
specifications
WDR
0.047±5%
μF
Guaranteed
constants
*
7
R
W
When PE1 has open-drain output
specifications
WDR
680±1%
k
4 to 5.5
R
l
When PE1 has open-drain output
specifications
WDR
100±1%
Clear time (discharge) t
WCT
Clear period (charge) t
WCCY
See Figure 7.
WDR
40
μs
See Figure 7.
WDR
15
ms
W
Note: 1. When driven internally using the oscillator circuit shown in Figure 3 with guaranteed constants, values up to the amplitude of the generated
oscillation are allowed.
2. The average over a 100-ms period
3. The operating power-supply voltage VDD must be maintained from the point where a HALT instruction is executed until the point where the device
has fully entered the standby state. Also, applications must be designed so that no chattering (e.g. switch bounce) occurs on the PA3 pin during a
HALT instruction execution cycle.
4. When external clock is selected as the oscillator option, the OSC1 pin has Schmitt characteristics.
5. The values shown for fCFOSC are the frequencies for which oscillation is possible. The center frequency when a ceramic oscillator is used may
differ by about 1% from the nominal value listed by the manufacturer of the ceramic oscillator element. See the specifications of the ceramic
oscillator element for details.
6. Tcyc = 4
×
the system clock period
7. If this device is used in an environment subject to condensation, extra care is required concerning leakage between PE1 and adjacent pins and
leakage associated with external capacitors.
Continued from preceding page.
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