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參數(shù)資料
| 型號(hào)： | L80223 |
| 廠商： | LSI CORP |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | 10BASE-T/100BASE-TX/FX Ethernet Physical Layer Device (PHY)(10BASE-T/100BASE-TX/FX 以太網(wǎng)物理層處理器) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | LQFP-64 |
| 文件頁(yè)數(shù)： | 44/192頁(yè) |
| 文件大小： | 1306K |
| 代理商： | L80223 |
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Draft 6/5/00
2-24
Functional Description
Copyright 2000 by LSI Logic Corporation. All rights reserved.
2.2.8 Twisted-Pair Receivers
The device is capable of operating at either 10- or 100-Mbits/s. This
section describes the twisted-pair receivers and squelch operation for
both modes of operation.
2.2.8.1 100 Mbits/s TP Receiver
The TP receiver detects input signals from the twisted-pair input and
converts them to a digital data bit stream ready for clock and data
recovery. The receiver can reliably detect 100BASE-TX compliant
transmitter data that has been passed through 0 to 100 meters of
100
category 5 UTP or 150-ohm STP cable.
The 100 Mbits/s receiver consists of an adaptive equalizer, baseline
wander correction circuit, comparators, and an MLT3 decoder. The TP
inputs first go to an adaptive equalizer. The adaptive equalizer
compensates for the low-pass characteristics of the cable, and can adapt
and compensate for 0 to 100 meters of category 5, 100-ohm or 150-ohm
STP cable. The baseline wander correction circuit restores the DC
component of the input waveform that the external transformers have
removed. The comparators convert the equalized signal back to digital
levels and qualify the data with the squelch circuit. The MLT3 decoder
takes the three-level MLT3 encoded output data from the comparators
and converts it to normal digital data to be used for clock and data
recovery.
2.2.8.2 10 Mbits/s TP Receiver
The 10 Mbits/s receiver detects input signals from the twisted-pair cable
that are within the template shown in
Figure 2.5
The TP inputs are
biased by internal resistors and go through a low-pass filter designed to
eliminate any high-frequency input noise. The output of the receive filter
goes to two different types of comparators: squelch and zero crossing.
The squelch comparator determines whether the signal is valid, and the
zero crossing comparator senses the actual data transitions after the
signal is determined to be valid. The output of the squelch comparator
goes to the squelch circuit and is also used for link pulse detection, SOI
detection, and reverse polarity detection. The output of the zero-crossing
comparator is used for clock and data recovery in the Manchester
decoder.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| L80600 | L80600 10/100/1000 Mbits/s Ethernet PHY technical manual 3/01 |
| L811-1X1T-03 | 1port.None LEDs.low profile RJ45 10/100Base-TX |
| L82-510 | Logic IC |
| L82-511 | Logic IC |
| L82-512 | Logic IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L80223/A | 制造商:LSI Corporation 功能描述:PN may be NE DW |
| L80223/C | 制造商:LSI Corporation 功能描述:PN may be NE DW |
| L80223/D | 制造商:LSI Corporation 功能描述:PHY 1-CH 10Mbps/100Mbps 64-Pin LQFP |
| L80223/D-E6 | 制造商:LSI Corporation 功能描述:TRANSITION TO P/N 68032B1 - Bulk |
| L80223/D-LEADFREE | 制造商:LSI Corporation 功能描述: |
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