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參數(shù)資料
| 型號(hào)： | L80223 |
| 廠商： | LSI CORP |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | 10BASE-T/100BASE-TX/FX Ethernet Physical Layer Device (PHY)(10BASE-T/100BASE-TX/FX 以太網(wǎng)物理層處理器) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | LQFP-64 |
| 文件頁(yè)數(shù)： | 114/192頁(yè) |
| 文件大?。?/td> | 1306K |
| 代理商： | L80223 |
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Draft 6/5/00
5-6
Management Interface
Copyright 2000 by LSI Logic Corporation. All rights reserved.
5.4 Frame Structure
The structure of the serial port frame is shown in
Figure 5.2
and a timing
diagram is shown in
Figure 5.1
. Each serial port access cycle consists
of 32 bits, exclusive of idle. The first 16 bits of the serial port cycle are
always write bits and are used for control and addressing. The last 16
bits are data that is written to or read from a data register.
The first two bits in
Figure 5.2
and
Figure 5.1
are start bits (ST[1:0]) and
must be written as a 0b01 for the serial port cycle to continue. The next
two bits are the READ and WRITE bits, which determine whether a
registers is being read or written. The next five bits are the PHY device
address bits (PHYAD[4:0]), and they must match the inverted values
latched from the MDA[4:0]n pins during the power on reset time for
access to continue.
The next five bits are register address select (REGAD[4:0]) bits, which
select one of the 11 registers for access. The next two bits are
turnaround (TA) bits, which are not actual register bits but provide the
device extra time to switch the MDIO pin function from a write pin to a
read pin, if necessary. The final 16 bits of the MI serial port cycle are
written to or read from the specific data register that the register address
bits (REGAD[4:0]) designate.
Figure 5.2
shows the MI frame structure.
IDLE
Idle Pattern
These bits are an idle pattern. The device does not
initiate an MI cycle until it detects an idle pattern of at
least 32 consecutive ones.
W
ST[1:0]
Start Bits
When ST[1:0] = 01, a MI serial port access cycle starts.
W
READ
Read Select
When the READ bit is 1, it designates a read cycle.
W
WRITE
Write Select
When the WRITE bit is 1, it designates a write cycle.
W
Figure 5.2
MI Serial Frame Structure
IDLE
ST[1:0]
READ
WRITE
PHYAD[4:0]
REGAD[4:0]
TA[1:0]
D[15:0]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| L80600 | L80600 10/100/1000 Mbits/s Ethernet PHY technical manual 3/01 |
| L811-1X1T-03 | 1port.None LEDs.low profile RJ45 10/100Base-TX |
| L82-510 | Logic IC |
| L82-511 | Logic IC |
| L82-512 | Logic IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L80223/A | 制造商:LSI Corporation 功能描述:PN may be NE DW |
| L80223/C | 制造商:LSI Corporation 功能描述:PN may be NE DW |
| L80223/D | 制造商:LSI Corporation 功能描述:PHY 1-CH 10Mbps/100Mbps 64-Pin LQFP |
| L80223/D-E6 | 制造商:LSI Corporation 功能描述:TRANSITION TO P/N 68032B1 - Bulk |
| L80223/D-LEADFREE | 制造商:LSI Corporation 功能描述: |
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