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參數資料
| 型號： | L6726ATR |
| 廠商： | 意法半導體 |
| 英文描述： | Single phase PWM controller |
| 中文描述： | 單相PWM控制器 |
| 文件頁數： | 16/24頁 |
| 文件大?。?/td> | 399K |
| 代理商： | L6726ATR |
Application details
L6726A
16/24
depending on the output capacitor ESR. The DC Gain of the modulator is simply the input
voltage V
IN
divided by the peak-to-peak oscillator voltage
V
OSC
.
V
OUT
is scaled and transferred to FB node by the output resistor divider.
The compensation network closes the loop joining FB and COMP node with transfer
function ideally equal to -gm
·
Z
F
.
Compensation goal is to close the control loop assuring high DC regulation accuracy, good
dynamic performances and stability. To achieve this, the overall loop needs high DC gain,
high bandwidth and good phase margin.
High DC gain is achieved giving an integrator shape to compensation network transfer
function. Loop bandwidth (F
0dB
) can be fixed choosing the right R
F
; however, for stability, it
should not exceed F
SW
/2
π
. To achieve a good phase margin, the control loop gain has to
cross 0dB axis with -20dB/decade slope.
As an example,
Figure 9
shows an asymptotic bode plot of a type II compensation.
Figure 9.
Example of type II compensation.
Gain
[dB]
●
Open loop converter singularities:
a)
b)
●
Compensation Network singularities frequencies:
a)
b)
Log (Freq)
0dB
OTA
open loop
gain
closed loop
gain
compensation
gain
converter
open loop
gain
F
LC
F
ESR
F
Z
F
P
20log (gm·R
F
)
20log [V
IN
/
V
OSC
·R
OS
/(R
FB
+R
OS
)]
F
0dB
F
LC
2
π
L
C
OUT
------------------------------------
=
F
ESR
2
π
C
OUT
ESR
-------------------------------------------------
=
F
Z
2
π
R
F
C
F
-----------------------------------
=
F
P
2
π
R
F
C
F
P
C
P
+
---------------------
--------------------------------------------------------
=
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