參數(shù)資料
型號(hào): L6711
廠商: STMICROELECTRONICS
元件分類(lèi): 穩(wěn)壓器
英文描述: 2 A SWITCHING CONTROLLER, 178 kHz SWITCHING FREQ-MAX, PQFP48
封裝: 7 X 7 MM, 1 MM HEIGHT, TQFP-48
文件頁(yè)數(shù): 22/50頁(yè)
文件大小: 679K
代理商: L6711
Obsolete
Product(s)
- Obsolete
Product(s)
L6711
Dynamic VID transitions
29/50
11.1
VID_SEL = OPEN.
Selecting the VRD10.x DAC, the device checks for VID code modifications on the rising
edge of a clock that is three times the switching frequency of each phase and waits for a
confirmation on the following falling edge. Once the new code is stable, on the next rising
edge, the reference starts stepping up or down in LSB increments (12.5mV) every clock
cycle (still 3FSW) until the new VID code is reached. During the transition, VID code
changes are ignored; the device re-starts monitoring VID after the transition has finished on
the next rising edge available.
Warning:
if the new VID code is more than 1 LSB higher than the
previous, the device will execute the transition stepping the
reference with a frequency equal to 3FSW until the new code
has reached: for this reason it is recommended to carefully
control the VID change rate in order to carefully control the
slope of the output voltage variation.
Warning:
DVID sample and hold clock depends on the switching
frequency FSW. To correctly perform DVID transition so
following the VID change rate, it is required to have at least 2
complete cycles of the FDVID clock between every VID
transition. If the VID update-rate is, for example, 5
s, the
minimum operating frequency results to be FSW > 133kHz.
Figure 14.
Dynamic VID Transition, Hammer DAC
4 Step VID Transition - Hammer DAC
t
VID
Sample
d
VID
Change
d
VID
Sample
d
VID [0,5]
Int. Reference
Vout
Tsw
Ref
Mo
v
ed
(
1)
Ref
Mo
v
ed
(
2)
Ref
Mo
v
ed
(
3)
Ref
Mo
v
ed
(
4)
VID
Sample
d
t
VID
Stab
le
VID
Sample
d
VID Clock
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