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Current reading and current sharing control loop
L6711
20/50
50
A offset allows negative current reading, enabling the device to check for dangerous
returning current between the phases assuring the complete current equalization. From the
current information of each phase, information about the total current delivered (IDROOP =
IINFO1 + IINFO2 + IINFO3) and the average current for each phase (IAVG = (IINFO1 + IINFO2 +
IINFO3)/3 ) is taken. IINFOX is then compared to IAVG to give the correction to the PWMx
output in order to equalize the current carried by the three phases.
Figure 6.
Current reading across LS mosfet: timing (left) and circuit (right) for each
phase.
7.2
Inductor current reading
Shorting CS_SEL pin to SGND, the current flowing trough each phase is read using the
voltage drop across the output inductor or across a sense resistor (RSENSE) in its series and
internally converted into a current. The transconductance ratio is issued by the external
resistor Rg placed outside the chip between CSx- and CSx+ pins toward the reading points
The current sense circuit always tracks the current sensed and still sources a constant 50
A
current from the CSx+ pin: this pin is used as a reference keeping the CSx- pin to this
voltage. To correctly reproduce the inductor current an R-C filtering network must be
introduced in parallel to the sensing element.
The current that flows from the CSx- pin is then given by the following equation (See
FigureWhere IPHASEx is the current carried by the relative phase.
Considering now to match the time constant between the inductor and the R-C filter applied
(Time constant mismatches cause the introduction of poles into the current reading network
causing instability. Moreover, it is also important for the load transient response and to let
the system show resistive equivalent output impedance), it results:
where
IINFOx is the current information reproduced internally.
50
A offset allows negative current reading, enabling the device to check for dangerous
returning current between the phases assuring the complete current equalization. From the
000000000
IPHASEx
ILSx
IINFOx
TTRACK
TSW
CSx+
CSx-
LGATEx
IPHASEx
50
A
ICSx-
Rg
I
CSx-
50
A
R
L
R
g
-------
1s
L
R
L
-------
+
1s R
gR C
() Cg
+
------------------------------------------------
I
PHASEx
+
=
R
gRC
() Cg
I
CSx-
≥
50
A
R
L
Rg
-------- IPHASEx
+
50
AI
INFOx
+
==
I
INFOx
I
PHASEx
R
L
Rg
--------
=