參數(shù)資料
型號: L5993
廠商: STMICROELECTRONICS
元件分類: 穩(wěn)壓器
英文描述: 1.5 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PDIP16
封裝: DIP-16
文件頁數(shù): 22/22頁
文件大?。?/td> 200K
代理商: L5993
ered at pin 1 and defines the upper extreme of the
duty cycle range, Dx (see pin 15 for Dx definition
and calculation).
In case V15 is connecte d to VREF, however, the
switching frequency of the system will be a half
fosc.
If the IC is to be synchronized to an external oscil-
lator, RT and CT should be selected for a fosc
lower than the master frequency in any condition
(typically, 10-20% ), depending on the tolerance
of RT and CT .
Pin 3. DC (Duty Cycle Control). By biasing this
pin with a voltage between 1 and 3 V it is possible
to set the maximum duty cycle between 0 and the
upper extreme Dx (see pin 15).
If Dmax is the desired maximum duty cycle, the
voltage V3 to be applied to pin 3 is:
V3 =5 - 2
(2-Dmax)
(4)
Dmax is determined by internal comparison be-
tween V3 and the oscillator ramp (see fig. 22),
thus in case the device is synchronized to an ex-
ternal frequency fext (and therefore the oscillator
amplitude is reduced), (4) changes into:
V3
= 5 4
exp
Dmax
RT
CT fext
(5)
A voltage below 1V will inhibit the driver output
stage. This could be used for a not-latched device
disable, for example in case of overvoltage pro-
tection (see application ideas).
If no limitation on the maximum duty cycle is re-
quired (i.e. DMAX =DX), the pin has to be left float-
ing. An internal pull-up (see fig. 22) holds the volt-
age above 3V. Should the pin pick up noise (e.g.
during ESD tests), it can be connected to VREF
through a 4.7k
resistor.
Pin 4. VREF (Reference Voltage). The device is
provided with an accurate voltage reference
(5V
±1.5%) able to deliver some mA to an external
circuit.
A small film capacitor (0.1
F typ.), connected
between this pin and SGND, is recommended to
ensure the stability of the generator and to prevent
noise from affectingthe reference.
Before device turn-on, this pin has a sink current
capability of 0.5mA.
+
-
R2
R3
R1
CLAMP
D1
50
RT
CT
D
R
Q
600
A
D97IN500B
VREF
RCT
SYNC
CLK
2
4
1
Figure 21. Oscillator and synchronization internal schematic.
+
-
R2
R1
RT
C
T
D97IN711A
VREF
RCT
DC
TO PWM LOGIC
4
3
2
23K
28K
3
A
Figure 22. Duty cycle control.
L5993
9/22
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