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參數(shù)資料
| 型號： | KSZ9021GN-EVAL |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 6/53頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR KSZ9021GN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，以太網(wǎng)控制器（PHY 和 MAC） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ9021GN |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | 576-3789-ND - TXRX GIG ETH GMII/MII 64-QFN KSZ9021GN TR-ND - TXRX ETHERNET GB GMII/MII 64MLF 576-3635-ND - TXRX ETHERNET GB GMII/MII 64-MLF |
| 其它名稱： | 576-3873 |
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Micrel, Inc.
KSZ9021GN
September 2010
14
M9999-091010-1.1
Strapping Options
Pin Number
Pin Name
Type
(1)
Pin Function
48
17
19
PHYAD2
PHYAD1
PHYAD0
I/O
The PHY Address, PHYAD[2:0], is latched at power-up / reset and is configurable to
any value from 1 to 7. Each PHY address bit is configured as follows:
Pull-up = 1
Pull-down = 0
PHY Address bits [4:3] are always set to ‘00’.
39
41
43
44
MODE3
MODE2
MODE1
MODE0
I/O
The MODE[3:0] strap-in pins are latched at power-up / reset and are defined as
follows:
MODE[3:0]
Mode
0000
Reserved – not used
0001
GMII / MII Mode
0010
Reserved – not used
0011
Reserved – not used
0100
NAND Tree Mode
0101
Reserved – not used
0110
Reserved – not used
0111
Chip Power Down Mode
1000
Reserved – not used
1001
Reserved – not used
1010
Reserved – not used
1011
Reserved – not used
1100
Reserved – not used
1101
Reserved – not used
1110
Reserved – not used
1111
Reserved – not used
45
CLK125_EN
I/O
CLK125_EN is latched at power-up / reset and is defined as follows:
Pull-up = Enable 125MHz Clock Output
Pull-down = Disable 125MHz Clock Output
Pin 55 (CLK125_NDO) provides the 125MHz reference clock output option for use by
the MAC.
55
LED_MODE
I/O
LED_MODE is latched at power-up / reset and is defined as follows:
Pull-up = Single LED Mode
Pull-down = Tri-color Dual LED Mode
Note:
1.
I/O = Bi-directional.
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may be driven during
power-up or reset, and consequently cause the PHY strap-in pins on the GMII/MII signals to be latched to the incorrect
configuration. In this case, it is recommended to add external pull-ups/pull-downs on the PHY strap-in pins to ensure
the PHY is configured to the correct pin strap-in mode.
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參數(shù)描述 |
|---|---|
| KSZ9021GNI | 功能描述:以太網(wǎng) IC Gigabit Ethernet Transceiver with GMII/MII, I-Temp RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ9021GQ | 功能描述:以太網(wǎng) IC Gigabit Ethernet Transceiver with GMII/MII, Lead Free RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ9021GQI | 功能描述:以太網(wǎng) IC Gigabit Ethernet Transceiver w/ GMII/MII, I-Temp RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ9021RL | 功能描述:以太網(wǎng) IC Gigabit Ethernet Transceiver with GMII RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| KSZ9021RL-EVAL | 制造商:Micrel Inc 功能描述:GIGABIT ETHERNET TRANSCEIVER W 制造商:Micrel Inc 功能描述:KIT EVALUATION FOR KSZ9021RL |
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