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參數(shù)資料
| 型號(hào)： | KSZ9021GN-EVAL |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 5/53頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR KSZ9021GN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，以太網(wǎng)控制器（PHY 和 MAC） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | KSZ9021GN |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | 576-3789-ND - TXRX GIG ETH GMII/MII 64-QFN KSZ9021GN TR-ND - TXRX ETHERNET GB GMII/MII 64MLF 576-3635-ND - TXRX ETHERNET GB GMII/MII 64-MLF |
| 其它名稱： | 576-3873 |
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Micrel, Inc.
KSZ9021GN
September 2010
13
M9999-091010-1.1
Pin Number
Pin Name
Type
(1)
Pin Function
51
MDIO
Ipu/O
Management Data Input / Output
This pin is synchronous to MDC (pin 50) and requires an external pull-up resistor
to DVDDH (digital VDD) in a range from 1.0KΩ to 4.7KΩ.
52
COL
O
GMII Mode:
GMII COL (Collision Detected) Output
MII Mode:
MII COL (Collision Detected) Output
53
INT_N
O
Interrupt Output
This pin provides a programmable interrupt output and requires an external pull-up
resistor to DVDDH (digital VDD) in a range from 1.0KΩ to 4.7KΩ when active low.
Register 1Bh is the Interrupt Control/Status Register for programming the interrupt
conditions and reading the interrupt status. Register 1Fh bit 14 sets the interrupt
output to active low (default) or active high.
54
DVDDL
P
1.2V digital VDD
55
CLK125_NDO /
LED_MODE
I/O
125MHz Clock Output
This pin provides a 125MHz reference clock output option for use by the MAC. /
Config Mode:
The pull-up/pull-down value is latched as LED_MODE during
power-up / reset. See “Strapping Options” section for details.
56
RESET_N
Ipu
Chip Reset (active low)
Hardware pin configurations are strapped-in at the de-assertion (rising edge) of
RESET_N. See “Strapping Options” section for more details.
57
TX_CLK
O
MII Mode:
MII TX_CLK (Transmit Reference Clock) Output
58
LDO_O
O
On-chip 1.2V LDO Controller Output
This pin drives the input gate of a P-channel MOSFET to generate 1.2V for the
chip’s core voltages. If 1.2V is provided by the system and this pin is not used, it
can be left floating.
59
AVDDL_PLL
P
1.2V analog VDD for PLL
60
XO
O
25MHz Crystal feedback
This pin is a no connect if oscillator or external clock source is used.
61
XI
I
Crystal / Oscillator / External Clock Input
25MHz +/-50ppm tolerance
62
AVDDH
P
3.3V analog VDD
63
ISET
I/O
Set transmit output level
Connect a 4.99K
Ω 1% resistor to ground on this pin.
64
AGNDH
Gnd
Analog ground
PADDLE
P_GND
Gnd
Exposed Paddle on bottom of chip
Connect P_GND to ground.
Note:
1. P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input with internal pull-up.
Ipu/O = Input with internal pull-up / Output.
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