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參數(shù)資料
| 型號(hào)： | KSZ8895RQI |
| 廠商： | Micrel Inc |
| 文件頁(yè)數(shù)： | 68/119頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC 10/100-T 5 PORT SW 128PQFP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 系列： | * |
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PIC16(L)F1782/3
DS41579C-page 52
Preliminary
2011-2012 Microchip Technology Inc.
5.4
Low-Power Brown-Out Reset
(LPBOR)
The Low-Power Brown-Out Reset (LPBOR) is an
essential part of the Reset subsystem. Refer to
Figure 5-1 to see how the BOR interacts with other
modules.
The LPBOR is used to monitor the external VDD pin.
When too low of a voltage is detected, the device is
held in Reset. When this occurs, a register bit (BOR) is
changed to indicate that a BOR Reset has occurred.
The same bit is set for both the BOR and the LPBOR.
Refer to Register 5-2.
5.4.1
ENABLING LPBOR
The LPBOR is controlled by the LPBOR bit of
Configuration Words. When the device is erased, the
LPBOR module defaults to disabled.
5.4.1.1
LPBOR Module Output
The output of the LPBOR module is a signal indicating
whether or not a Reset is to be asserted. This signal is
OR’d together with the Reset signal of the BOR mod-
ule to provide the generic BOR signal, which goes to
the PCON register and to the power control block.
5.5
MCLR
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Words and the LVP bit of
Configuration Words (Table 5-2).
5.5.1
MCLR ENABLED
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
5.5.2
MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 13.9 “PORTE Regis-
ters” for more information.
5.6
Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 11.0
“Watchdog Timer (WDT)” for more information.
5.7
RESET Instruction
A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Table 5-4
for default conditions after a RESET instruction has
occurred.
5.8
Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
Words. See Section 5.8 “Stack Overflow/Underflow
Reset” for more information.
5.9
Programming Mode Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
5.10
Power-up Timer
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
The Power-up Timer is controlled by the PWRTE bit of
Configuration Words.
5.11
Start-up Sequence
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1.
Power-up Timer runs to completion (if enabled).
2.
Oscillator start-up timer runs to completion (if
required for oscillator source).
3.
MCLR must be released (if enabled).
The total time-out will vary based on oscillator configu-
ration and Power-up Timer configuration. See
Clock Monitor)” for more information.
The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low
long enough, the Power-up Timer and oscillator
start-up timer will expire. Upon bringing MCLR high, the
device
will
begin
execution
immediately
(see
Figure 5-3). This is useful for testing purposes or to
synchronize more than one device operating in parallel.
TABLE 5-2:
MCLR CONFIGURATION
MCLRE
LVP
MCLR
00
Disabled
10
Enabled
x1
Enabled
Note:
A Reset does not drive the MCLR pin low.
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