參數(shù)資料
型號： KSZ8895RQI
廠商： Micrel Inc
文件頁數(shù)： 103/119頁
文件大?。?/td> 0K
描述： IC 10/100-T 5 PORT SW 128PQFP
標準包裝： 66
系列： *
PIC16(L)F1782/3
DS41579C-page 84
Preliminary
2011-2012 Microchip Technology Inc.
8.6
Register Definitions: Interrupt Control
REGISTER 8-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0
R-0/0
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all active interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
TMR0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4
INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3
IOCIE: Interrupt-on-Change Enable bit
1 = Enables the interrupt-on-change
0 = Disables the interrupt-on-change
bit 2
TMR0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed
0 = TMR0 register did not overflow
bit 1
INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred
0 = The INT external interrupt did not occur
bit 0
IOCIF: Interrupt-on-Change Interrupt Flag bit(1)
1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins have changed state
Note 1:
The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCBF register
have been cleared by software.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User
software
should
ensure
the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
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