參數(shù)資料
型號(hào)： KSZ8863FLLI
廠商： Micrel Inc
文件頁(yè)數(shù)： 48/106頁(yè)
文件大?。?/td> 0K
描述： IC ETHERNET SWITCH 3PORT 48-LQFP
標(biāo)準(zhǔn)包裝： 250
控制器類型： 以太網(wǎng)開關(guān)控制器
接口： MII
電源電壓： 1.8V，2.5V，3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
配用： 576-3866-ND - BOARD EVALUATION FOR KSZ8863FLL
其它名稱： 576-3750
PIC16C72 Series
1998 Microchip Technology Inc.
Preliminary
DS39016A-page 45
8.3.1
OPERATION OF SSP MODULE IN SPI
MODE - PIC16CR72
A block diagram of the SSP Module in SPI Mode is
shown in Figure 8-6.
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
Serial Data Out (SDO)
RC5/SDO
Serial Data In (SDI)
RC4/SDI/SDA
Serial Clock (SCK)
RC3/SCK/SCL
Additionally a fourth pin may be used when in a slave
mode of operation:
Slave Select (SS)
RA5/SS/AN4
When initializing the SPI, several options need to be
specied. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the fol-
lowing to be specied:
Master Operation (SCK is the clock output)
Slave Mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Clock Edge (Output data on rising/falling edge of
SCK)
Clock Rate (master operation only)
Slave Select Mode (Slave mode only)
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON<5>) must be set. To reset or recongure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
ister, and then set bit SSPEN. This congures the SDI,
SDO, SCK, and SS pins as serial port pins. For the pins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register) appro-
priately programmed. That is:
SDI must have TRISC<4> set
SDO must have TRISC<5> cleared
SCK (master operation) must have TRISC<3>
cleared
SCK (Slave mode) must have TRISC<3> set
SS must have TRISA<5> set
FIGURE 8-6:
SSP BLOCK DIAGRAM
(SPI MODE)(PIC16CR72)
Note:
When the SPI is in Slave Mode with SS pin
control enabled, (SSPCON<3:0> = 0100)
the SPI module will reset if the SS pin is set
to VDD.
Note:
If the SPI is used in Slave Mode with
CKE = '1', then the SS pin control must be
enabled.
Read
Write
Internal
data bus
RC4/SDI/SDA
RC5/SDO
RA5/SS/AN4
RC3/SCK/
SSPSR reg
SSPBUF reg
SSPM3:SSPM0
bit0
shift
clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 output
TCY
Prescaler
4, 16, 64
TRISC<3>
2
Edge
Select
2
4
SCL
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