參數(shù)資料
型號： KSZ8863FLLI
廠商： Micrel Inc
文件頁數(shù)： 36/106頁
文件大小： 0K
描述： IC ETHERNET SWITCH 3PORT 48-LQFP
標準包裝： 250
控制器類型： 以太網(wǎng)開關(guān)控制器
接口： MII
電源電壓： 1.8V，2.5V，3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
配用： 576-3866-ND - BOARD EVALUATION FOR KSZ8863FLL
其它名稱： 576-3750
PIC16C72 Series
DS39016A-page 34
Preliminary
1998 Microchip Technology Inc.
7.1
Capture Mode
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is dened as:
every falling edge
every rising edge
every 4th rising edge
every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request ag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
7.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be cong-
ured as an input by setting the TRISC<2> bit.
FIGURE 7-2:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
7.1.2
TIMER1 MODE SELECTION
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work.
7.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the ag bit CCP1IF following any such
change in operating mode.
7.1.4
CCP PRESCALER
There are four prescaler settings, specied by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in capture mode,
the prescaler counter is cleared. This means that any
reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the rst capture may be from
a non-zero prescaler. Example 7-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 7-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF
CCP1CON
;Turn CCP module off
MOVLW
NEW_CAPT_PS
;Load the W reg with
; the new prescaler
; mode value and CCP ON
MOVWF
CCP1CON
;Load CCP1CON with this
; value
Note:
If the RC2/CCP1 is congured as an out-
put, a write to the port can cause a capture
condition.
CCPR1H
CCPR1L
TMR1H
TMR1L
Set ag bit CCP1IF
(PIR1<2>)
Capture
Enable
Q’s
CCP1CON<3:0>
RC2/CCP1
Prescaler
÷ 1, 4, 16
and
edge detect
Pin
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