參數(shù)資料
型號(hào)： KSZ8842-PMBL AM TR
廠商： Micrel Inc
文件頁(yè)數(shù)： 76/119頁(yè)
文件大小： 0K
描述： IC ETHERNET SW 2PORT 100LFBGA
標(biāo)準(zhǔn)包裝： 1,000
控制器類型： 以太網(wǎng)開關(guān)控制器
接口： PCI
電源電壓： 3.1 V ~ 3.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LFBGA
供應(yīng)商設(shè)備封裝： 100-LFBGA
包裝： 帶卷 (TR)
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Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
6
M9999-100207-1.5
TOS Priority Control Register 4 (Offset 0x486): TOSR4 .............................................................................................. 60
TOS Priority Control Register 5 (Offset 0x488): TOSR5 .............................................................................................. 61
TOS Priority Control Register 6 (Offset 0x48A): TOSR6.............................................................................................. 62
TOS Priority Control Register 7 (Offset 0x490): TOSR7 .............................................................................................. 62
TOS Priority Control Register 8 (Offset 0x492): TOSR8 .............................................................................................. 63
Reserved (Offset 0x0494 - 0x049A) ............................................................................................................................. 63
Indirect Access Control Register (Offset 0x04A0): IACR ............................................................................................. 64
Indirect Access Data Register 1 (Offset 0x04A2): IADR1 ............................................................................................ 64
Indirect Access Data Register 2 (Offset 0x04A4): IADR2 ............................................................................................ 64
Indirect Access Data Register 3 (Offset 0x04A6): IADR3 ............................................................................................ 64
Indirect Access Data Register 4 (Offset 0x04A8): IADR4 ............................................................................................ 64
Indirect Access Data Register 5 (Offset 0x04AA): IADR5 ............................................................................................ 65
Reserved (Offset 0x04B0 - 0x04BA) ............................................................................................................................ 65
Reserved (Offset 0x04C0 –0x04CF) ............................................................................................................................ 65
PHY 1 MII Basic Control Register (Offset 0x04D0): P1MBCR ..................................................................................... 65
PHY 1 MII Basic Status Register (Offset 0x04D2): P1MBSR....................................................................................... 66
PHY 1 PHYID Low Register (Offset 0x04D4): PHY1ILR.............................................................................................. 67
PHY 1 PHYID High Register (Offset 0x04D6): PHY1IHR .......................................................................................... 67
PHY 1 Auto-Negotiation Advertisement Register (Offset 0x04D8): P1ANAR .............................................................. 67
PHY 1 Auto-Negotiation Link Partner Ability Register (Offset 0x04DA): P1ANLPR..................................................... 68
PHY 2 MII Basic Control Register (Offset 0x04E0): P2MBCR ..................................................................................... 68
PHY 2 MII Basic Status Register (Offset 0x04E2): P2MBSR....................................................................................... 69
PHY 2 PHYID Low Register (Offset 0x04E4): PHY2ILR .............................................................................................. 70
PHY 2 PHYID High Register (Offset 0x04E6): PHY2IHR............................................................................................. 70
PHY 2 Auto-Negotiation Advertisement Register (Offset 0x04E8): P2ANAR .............................................................. 70
PHY 2 Auto-Negotiation Link Partner Ability Register (Offset 0x04EA): P2ANLPR..................................................... 71
PHY1 LinkMD Control/Status (Offset 0x04F0): P1VCT................................................................................................ 72
PHY1 Special Control/Status Register (Offset 0x04F2): P1PHYCTRL ....................................................................... 72
PHY2 LinkMD Control/Status (Offset 0x04F4): P2VCT................................................................................................ 73
PHY2 Special Control/Status Register (Offset 0x04F6): P2PHYCTRL ........................................................................ 73
Reserved (Offset 0x04F8 - 0x04FA)............................................................................................................................. 73
Port 1 Control Register 1 (Offset 0x0500): P1CR1....................................................................................................... 74
Port 1 Control Register 2 (Offset 0x0502): P1CR2....................................................................................................... 75
Port 1 VID Control Register (Offset 0x0504): P1VIDCR............................................................................................... 76
Port 1 Control Register 3 (Offset 0x0506): P1CR3....................................................................................................... 76
Port 1 Ingress Rate Control Register (Offset 0x0508): P1IRCR................................................................................... 77
Port 1 Egress Rate Control Register (Offset 0x050A): P1ERCR ................................................................................. 79
Port 1 PHY Special Control/Status, LinkMD (Offset 0x0510): P1SCSLMD ................................................................. 81
Port 1 Control Register 4 (Offset 0x0512): P1CR4....................................................................................................... 82
Port 1 Status Register (Offset 0x0514): P1SR ............................................................................................................. 83
Port 1 Reserved (Offset 0x0516 – 0x051A).................................................................................................................. 84
Port 2 Control Register 1 (Offset 0x0520): P2CR1....................................................................................................... 84
Port 2 Control Register 2 (Offset 0x0522): P2CR2....................................................................................................... 85
Port 2 VID Control Register (Offset 0x0524): P2VIDCR............................................................................................... 86
Port 2 Control Register 3 (Offset 0x0526): P2CR3....................................................................................................... 87
Port 2 Ingress Rate Control Register (Offset 0x0528): P2IRCR................................................................................... 87
Port 2 Egress Rate Control Register (Offset 0x052A): P2ERCR ................................................................................. 89
Port 2 PHY Special Control/Status, LinkMD (Offset 0x0530): P2SCSLMD ................................................................. 92
Port 2 Control Register 4 (Offset 0x0532): P2CR4....................................................................................................... 92
Port 2 Status Register (Offset 0x0534): P2SR ............................................................................................................. 94
Port 2 Reserved (Offset 0x0536 – 0x053A).................................................................................................................. 95
Host Control Register 1 (Offset 0x0540): P3CR1 ......................................................................................................... 95
Host Control Register 2 (Offset 0x0542): P3CR2 ......................................................................................................... 96
Host VID Control Register (Offset 0x0544): P3VIDCR................................................................................................. 97
Host Control Register 3 (Offset 0x0546): P3CR3 ......................................................................................................... 97
Host Ingress Rate Control Register (Offset 0x0548): P3IRCR..................................................................................... 98
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KSZ8842-PMBL-EVAL 功能描述:以太網(wǎng)開發(fā)工具 2+1 Port 10/100 Ethernet Switch with 32b/33MHz PCI Interface (BGA Version) Eval Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓:
KSZ8842-PMBL-TR 功能描述:Ethernet Switch 10/100 Base-T/TX PHY PCI Interface 100-LFBGA (9x9) 制造商:microchip technology 系列:- 包裝:剪切帶（CT） 零件狀態(tài):停產(chǎn) 協(xié)議:以太網(wǎng) 功能:開關(guān) 接口:PCI 標(biāo)準(zhǔn):10/100 Base-T/TX PHY 電壓 - 電源:3.1 V ~ 3.5 V 電流 - 電源:122mA 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LFBGA 供應(yīng)商器件封裝:100-LFBGA（9x9） 標(biāo)準(zhǔn)包裝:1
KSZ8842-PMQL 功能描述:以太網(wǎng) IC 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI bus interface(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
KSZ8842-PMQL-EVAL 功能描述:以太網(wǎng)開發(fā)工具 KSZ8842-PMQL Evaluation Board RoHS:否 制造商:Micrel 產(chǎn)品:Evaluation Boards 類型:Ethernet Transceivers 工具用于評(píng)估:KSZ8873RLL 接口類型:RMII 工作電源電壓:
KSZ8842-PMQLI 功能描述:以太網(wǎng) IC 2-Port Ethernet Switch/Repeater + 32-bit/33MHz PCI bus interface, Ind Temp (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
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