參數(shù)資料
型號: KSZ8842-PMBL AM TR
廠商: Micrel Inc
文件頁數(shù): 40/119頁
文件大?。?/td> 0K
描述: IC ETHERNET SW 2PORT 100LFBGA
標準包裝: 1,000
控制器類型: 以太網(wǎng)開關控制器
接口: PCI
電源電壓: 3.1 V ~ 3.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LFBGA
供應商設備封裝: 100-LFBGA
包裝: 帶卷 (TR)
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
27
M9999-100207-1.5
Spanning Tree
Process
PTF1
IGMP Process
Port Mirror
Process
Port VLAN
Membership
Check
PTF2
- Check receiving port's receive enable bit
- Check destination port's transmit enable bit
- Check whether packets are special (BPDU)
or specified
- RX Mirror
- TX Mirror
- RX or TX Mirror
- RX and TX Mirror
- Applied to MAC #1 and MAC #2
- IGMP will be forwarded to the host port
Figure 8. Destination Address Resolution Flow Chart, Stage 2
The KSZ8842-PMQL/PMBL will not forward the following packets:
1.
Error packets.
These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet
errors.
2.
802.3x pause frames.
The KSZ8842-PMQL/PMBL intercepts these packets and performs flow control.
3.
"Local" packets.
Based on destination address (DA) lookup. If the destination port from the lookup table matches the port from
which the packet originated, the packet is defined as "local."
Switching Engine
The KSZ8842-PMQL/PMBL features a high-performance switching engine to move data to and from the MAC’s packet
buffers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency.
The switching engine has a 32KB internal frame buffer. This resource is shared between all the ports. There are a total
of 256 buffers available. Each buffer is sized at 128B.
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