參數(shù)資料
型號: KSZ8842-16MQL-EVAL
廠商: Micrel Inc
文件頁數(shù): 73/141頁
文件大?。?/td> 0K
描述: BOARD EVALUATION KSZ8842-16MQL
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8842-16MQL
主要屬性: 2 個端口,100BASE-TX/10BASE-T,管理型
次要屬性: 8/16 位接口,LinkMD 線纜診斷
已供物品: 板,CD,文檔,電源
產(chǎn)品目錄頁面: 1114 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 576-3076-ND - IC MAC CTLR 2PORT ETH 100-LFBGA
KSZ8842-32MQLA6-ND - IC SWITCH 10/100 32BIT 128PQFP
576-1479-ND - IC SWITCH 10/100 32BIT 128PQFP
576-1478-5-ND - IC SWITCH 10/100 16BIT 128PQFP
其它名稱: 576-1634
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
37
M9999-102207-1.9
physical data bus. For example, for a 32-bit system/host data bus, it allows 8, 16, and 32-bit data transfers (KSZ8842-
32MQL); for a 16-bit system/host data bus, it allows 8 and 16-bit data transfers (KSZ8842-16MQL); and for 8-bit
system/host data bus, it only allows 8-bit data transfers (KSZ8842-16MQL).
Note that KSZ8842M does not support internal data byte-swap but it does support internal data word-swap. This means
that the system/host data bus HD[7:0] has to connect to both D[7:0] and D[15:8] for 8-bit data bus interfaces. However,
the system/host data bus HD[15:8] and HD[7:0] just connects to D[15:8] and D[7:0], respectively, for 16-bit data bus
interface; there is no need to connect HD[31:24] and HD[23:16] to D[31:24] and D[23:16].
Table 2 describes the BIU signal grouping.
Signal
Type
(1)
Function
Common Signals
A[15:1]
I
Address
AEN
I
Address Enable
Address Enable asserted indicates memory address on the bus for DMA
access and since the device is an I/O device, address decoding is only enabled
when AEN is low.
BE3N, BE2N,
BE1N, BE0N
I
Byte Enable
BE0N
BE1N
BE2N
BE3N
Description
0
32-bit access (32-bit bus only)
0
1
Lower 16-bit (D[15:0]) access
1
0
Higher 16-bit (D[31:16]) access
(32-bit bus only)
0
1
Byte 0 (D[7:0]) access
1
0
1
Byte 1 (D[15:8]) access
1
0
1
Byte 2 (D[23:16]) access (32-bit
bus only)
1
0
Byte 3 (D[31:24]) access (32-bit
bus only)
Note 1: BE3N, BE2N, BE1N and BE0N are ignored when DATACSN is low
because 32 bit transfers are assumed.
Note 2: BE2N and BE3N are valid only for the KSZ8842-32 mode, and are NC
for the KSZ8842-16 mode.
D[31:16]
I/O
Data
For KSZ8842-32 Mode only
D[15:0]
I/O
Data
For both KSZ8842-32 and KSZ8842-16 Modes
ADSN
I
Address Strobe
The rising edge of ADSN is used to latch A[15:1], AEN, BE3N, BE2N, BE1N
and BE0N.
LDEVN
O
Local Device
This signal is a combinatorial decode of AEN and A[15:4], The A[15:4] is used
to compare against the Base Address Register.
DATACSN
I
Data Register Chip Select (For KSZ8842-32 Mode only)
This signal is used for central decoding architecture (mostly for embedded
application). When asserted, the device’s local decoding logic is ignored and
the 32-bit access to QMU Data Register is assumed.
INTRN
O
Interrupt
Synchronous Transfer Signals
VLBUSN
I
VLBUSN = 0, VLBus-like cycle.
VLBUSN = 1, burst cycle (both host/system and KSZ8842 can insert wait state)
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