參數(shù)資料
型號(hào): KSZ8842-16MQL-EVAL
廠商: Micrel Inc
文件頁數(shù): 45/141頁
文件大?。?/td> 0K
描述: BOARD EVALUATION KSZ8842-16MQL
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng)控制器(PHY 和 MAC)
嵌入式:
已用 IC / 零件: KSZ8842-16MQL
主要屬性: 2 個(gè)端口,100BASE-TX/10BASE-T,管理型
次要屬性: 8/16 位接口,LinkMD 線纜診斷
已供物品: 板,CD,文檔,電源
產(chǎn)品目錄頁面: 1114 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: 576-3076-ND - IC MAC CTLR 2PORT ETH 100-LFBGA
KSZ8842-32MQLA6-ND - IC SWITCH 10/100 32BIT 128PQFP
576-1479-ND - IC SWITCH 10/100 32BIT 128PQFP
576-1478-5-ND - IC SWITCH 10/100 16BIT 128PQFP
其它名稱: 576-1634
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
139
M9999-102207-1.9
Acronyms and Glossary
BIU
Bus Interface Unit
The host interface function that performs code conversion, buffering,
and the like required for communications to and from a network.
BPDU Bridge Protocol Data Unit
A packet containing ports, addresses, etc. to make sure data being
passed through a bridged network arrives at its proper destination.
CMOS Complementary Metal Oxide Semiconductor
A common semiconductor manufacturing technique in which positive
and negative types of transistors are combined to form a current gate
that in turn forms an effective means of controlling electrical current
through a chip.
CRC Cyclic Redundancy Check
A common technique for detecting
data transmission errors. CRC for
Ethernet is 32 bits long.
Cut-through switch
A switch typically processes received packets by reading in the full
packet (storing), then processing the packet to determine where it
needs to go, then forwarding it. A cut-through switch simply reads in the
first bit of an incoming packet and forwards the packet. Cut-through
switches do not store the packet.
DA
Destination Address
The address to send packets.
DMA Direct Memory Access
A design in which memory on a chip is controlled independently of the
CPU.
EEPROM Electronically Erasable Programmable Read-only Memory
A design in which memory on a chip can be erased by exposing it to an
electrical charge.
EISA Extended Industry Standard Architecture
A
bus architecture designed for PCs using 80x86 processors, or an
Intel 80386, 80486 or Pentium microprocessor. EISA buses are 32
bits
wide and
support multiprocessing.
EMI
Electro-Magnetic Interference
A naturally occurring phenomena when the electromagnetic field of one
device disrupts, impedes or degrades the electromagnetic field of
another device by coming into proximity with it. In computer technology,
computer devices are susceptible to EMI because electromagnetic
fields are a byproduct of passing electricity through a wire. Data lines
that have not been properly shielded are susceptible to data corruption
by EMI.
FCS
Frame Check Sequence
See CRC.
FID
Frame or Filter ID
Specifies the frame identifier. Alternately is the filter identifier.
IGMP Internet Group Management Protocol
The protocol defined by RFC 1112 for IP multicast transmissions.
IPG
Inter-Packet Gap
A time delay between successive data packets mandated by the
network standard for protocol reasons. In Ethernet, the medium has to
be "silent" (i.e., no data transfer) for a short period of time before a node
can consider the network idle and start to transmit. IPG is used to
correct timing differences between a transmitter and receiver. During
the IPG, no data is transferred, and information in the gap can be
discarded or additions inserted without impact on data integrity.
ISI
Inter-Symbol Interference
T
he disruption of transmitted code caused by adjacent pulses
affecting or interfering with each other.
ISA
Industry Standard Architecture
A bus architecture used in the IBM PC/XT and
PC/AT.
Jumbo Packet
A packet larger than the standard Ethernet packet (1500 bytes). Large
packet sizes allow for more efficient use of bandwidth, lower overhead,
less processing, etc.
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