參數(shù)資料
型號(hào): KSZ8841-16MBL
廠商: Micrel Inc
文件頁(yè)數(shù): 71/105頁(yè)
文件大?。?/td> 0K
描述: IC MAC CTLR 1PORT ETH 100-LBGA
標(biāo)準(zhǔn)包裝: 260
控制器類型: 以太網(wǎng)控制器,MAC
接口: 總線
電源電壓: 3.1 V ~ 3.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LBGA
供應(yīng)商設(shè)備封裝: 100-LFBGA
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 1080 (CN2011-ZH PDF)
其它名稱: 576-3075
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
68
M9999-102207-1.6
Bank 18 Interrupt Enable Register (0x00): IER
This register enables the interrupts from the QMU and other sources.
Bit
Default Value
R/W
Description
15
0x0
RW
LCIE Link Change Interrupt Enable
When this bit is set, the link change interrupt is enabled.
When this bit is reset, the link change interrupt is disabled.
14
0x0
RW
TXIE Transmit Interrupt Enable
When this bit is set, the transmit interrupt is enabled.
When this bit is reset, the transmit interrupt is disabled.
13
0x0
RW
RXIE Receive Interrupt Enable
When this bit is set, the receive interrupt is enabled.
When this bit is reset, the receive interrupt is disabled.
12
0x0
RW
TXUIE Transmit Underrun Interrupt Enable
When this bit is set, the transmit underrun interrupt is enabled.
When this bit is reset, the transmit underrun interrupt is disabled.
11
0x0
RW
RXOIE Receive Overrun Interrupt Enable
When this bit is set, the Receive Overrun interrupt is enabled.
When this bit is reset, the Receive Overrun interrupt is disabled.
10
0x0
RW
RXEIE Receive Early Receive Interrupt Enable
When this bit is set, the Early Receive interrupt is enabled.
When this bit is reset, the Early Receive interrupt is disabled.
9
0x0
RW
TXPSIE Transmit Process Stopped Interrupt Enable
When this bit is set, the Transmit Process Stopped interrupt is enabled.
When this bit is reset, the Transmit Process Stopped interrupt is disabled.
8
0x0
RW
RXPSIE Receive Process Stopped Interrupt Enable
When this bit is set, the Receive Process Stopped interrupt is enabled.
When this bit is reset, the Receive Process Stopped interrupt is disabled.
7
0x0
RW
RXEFIE Receive Error Frame Interrupt Enable
When this bit is set, the Receive error frame interrupt is enabled.
When this bit is reset, the Receive error frame interrupt is disabled.
6-0
-
RO
Reserved.
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