參數(shù)資料
型號: KSZ8841-16MBL
廠商: Micrel Inc
文件頁數(shù): 16/105頁
文件大小: 0K
描述: IC MAC CTLR 1PORT ETH 100-LBGA
標準包裝: 260
控制器類型: 以太網(wǎng)控制器,MAC
接口: 總線
電源電壓: 3.1 V ~ 3.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LBGA
供應(yīng)商設(shè)備封裝: 100-LFBGA
包裝: 托盤
產(chǎn)品目錄頁面: 1080 (CN2011-ZH PDF)
其它名稱: 576-3075
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
October 2007
18
M9999-102207-1.6
Ball Number
Ball Name
Type
Ball Function
Active Low output signal, asserted when AEN is Low and A15-A4 decode to the
KSZ8841M address programmed into the high byte of the base address register.
LDEVN is a combinational decode of the Address and AEN signal.
B7
RDN
Ipd
Read Strobe Not
Asynchronous read strobe, active Low.
C7
EECS
Opu
EEPROM Chip Select
A6
ARDY
Opd
Asynchronous Ready
ARDY may be used when interfacing asynchronous buses to extend bus access
cycles. It is asynchronous to the host CPU or bus clock. This ball needs an
external 4.7K pull-up resistor.
B6
CYCLEN
Ipd
Cycle Not
For VLBus-like mode cycle signal; this ball follows the addressing cycle to signal
the command cycle.
For burst mode (32-bit interface only), this ball stays High for read cycles and
Low for write cycles.
A5
VLBUSN
Ipd
VLBus-like Mode
Pull-down or float: Bus interface is configured for synchronous mode.
Pull-up: Bus interface is configured for 8-bit or 16-bit asynchronous mode or
EISA-like burst mode.
B5
EEEN
Ipd
EEPROM Enable
EEPROM is enabled and connected when this ball is pull-up.
EEPROM is disabled when this ball is pull-down or no connect.
A4
P1LED3
Opd
Port 1 LED indicator
See the description in balls A10, B10, and C10.
B4
EEDO
Opd
EEPROM Data Out
This ball is connected to DI input of the serial EEPROM.
A3
EESK
Opd
EEPROM Serial Clock
A 4
s (OBCR[1:0]=11 on-chip bus speed @ 25 MHz) or 800 ns (OBCR[1:0]=00
on-chip bus speed @ 125 MHz) serial output clock cycle to load configuration
data from the serial EEPROM.
B3
EEDI
Ipd
EEPROM Data In
This ball is connected to DO output of the serial EEPROM when EEEN is pull-
up.
This ball can be pull-down for 8-bit bus mode, pull-up for 16-bit bus mode or
don’t care for 32-bit bus mode when EEEN is pull-down (without EEPROM).
C3
SWR
Ipd
Synchronous Write/Read
Write/Read signal for synchronous bus accesses. Write cycles when high and
Read cycles when low.
A2
AEN
Ipu
Address Enable
Address qualifier for the address decoding, active Low.
B2
WRN
Ipd
Write Strobe Not
Asynchronous write strobe, active Low.
A1
ADSN
Ipd
Address Strobe Not
For systems that require address latching, the rising edge of ADSN indicates the
latching moment of A15-A1 and AEN.
B1
PWRDN
Ipu
Full-chip power-down. Low = Power down; High or floating = Normal operation.
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