參數(shù)資料
型號(hào)： KSZ8692XPB
廠商： Micrel Inc
文件頁(yè)數(shù)： 24/42頁(yè)
文件大?。?/td> 0K
描述： IC ARM9 PHY 10/100MBPS 400-PBGA
標(biāo)準(zhǔn)包裝： 40
系列： KSZx692
應(yīng)用： 網(wǎng)絡(luò)和通信
核心處理器： ARM9
程序存儲(chǔ)器類型： 外部程序存儲(chǔ)器
控制器系列： KSZ
接口： EBI/EMI，以太網(wǎng)，I²C，I²S，PCI，SPI，UART/USART，USB
輸入/輸出數(shù)： 20
電源電壓： 1.235 V ~ 1.365 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 400-BGA
包裝： 托盤
供應(yīng)商設(shè)備封裝： 400-PBGA（24x24）
產(chǎn)品目錄頁(yè)面： 1080 (CN2011-ZH PDF)
其它名稱： 576-3537
Micrel, Inc.
KSZ8692MPB/KSZ8692XPB
March 2010
30
M9999-031810-4.0
Pin Number
Pin Name
Pin Type
Pin Description
A6, A7, E10,
C10
CBEN[3..0]
I/O
PCI Commands and Byte Enable, asserted Low.
The PCI command and byte enable signals are multiplexed on the same pins.
During the first clock cycle of a PCI transaction, the CBEN bus contains the
command for the transaction. The PCI transaction consists of the address
phases and one or more data phases. During the data phases of the
transaction, the bus carries the byte enable for the current data phases.
C8
PAR
I/O
Parity
PCI Bus parity is even across PAD[31:0] and CBEN[3:0].
The KSZ8692MPB/KSZ8692XPB generates PAR during the address phase
and write data phases as a bus master, and during read data phases as a
target. It checks for correct PAR during read data phase as a bus master,
during every address phase as a bus slave, and during write data phases as a
target.
D9
FRAMEN
I/O
PCI Bus Frame signal, asserted Low.
FRAMEN is an indication of an active PCI bus cycle. It is asserted at the
beginning of a PCI transaction, i.e. the address phase, and de-asserted before
the final transfer of the data phase of the transaction.
B8
IRDYN
I/O
PCI Initiator Ready signal, asserted Low.
This signal is asserted by a PCI master to indicate a valid data phase on the
PAD bus during data phases of a write transaction. In a read transaction, it
indicates that the master is ready to accept data from the target. A target will
monitor the IRDYN signal when a data phase is completed on any rising edge
of the PCI clock when both IRDYN and TRDYN are asserted. Wait cycles are
inserted until both IRDYN and TRDYN are asserted together.
E9
TRDYN
I/O
PCI Target Ready signal, asserted Low.
This signal is asserted by a PCI slave to indicate a valid data phase on the
PAD bus during data phases of a read transaction. In a write transaction, it
indicates that the slave is ready to accept data from the target. A PCI initiator
will monitor the TRDYN signal when a data phase is completed on any rising
edge of the PCI clock when both IRDYN and TRDYN are asserted. Wait
cycles are inserted until both IRDYN and TRDYN are asserted together.
A9
DEVSELN
I/O
PCI Device Select signal, asserted Low.
This signal is asserted when the KSZ8692MPB/KSZ8692XPB is selected as a
target during a bus transaction. When the KSZ8692MPB/KSZ8692XPB is the
initiator of the current bus access, it expects the target to assert DEVSELN
within 5 PCI bus cycles, confirming the access. If the target does not assert
DEVSELN within the required bus cycles, the KSZ8692MPB/KSZ8692XPB
aborts the bus cycle. As a target, the KSZ8692MPB/KSZ8692XPB asserts this
signal in a medium speed decode timing. (2 bus cycles)
B7
IDSEL
I
Initialization Device Select. It is used as a chip select during configuration
read and write transactions.
B9
STOPN
I/O
PCI Stop signal, asserted Low.
This signal is asserted by the PCI target to indicate to the bus master that it is
terminating the current transaction. The KSZ8692MPB/KSZ8692XPB
responds to the assertion of STOPN when it is the bus master, either to
disconnect, retry, or abort.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KSZ8695P 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Multi-Port PCI Gateway Solution(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
KSZ8695PI 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Multi-Port PCI Gateway Solution (Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
KSZ8695P-MDP-EVAL 功能描述:網(wǎng)絡(luò)開發(fā)工具 KSZ88695P-MDP Evaluation Board RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
KSZ8695P-MMB-EVAL 功能描述:網(wǎng)絡(luò)開發(fā)工具 KSZ8695P-MMB Evaluation Board RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
KSZ8695PX 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Integrated Multi-Port Gateway Solution w/ Single PCI(Lead Free) RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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