參數(shù)資料
型號(hào): KSZ8692XPB
廠商: Micrel Inc
文件頁(yè)數(shù): 22/42頁(yè)
文件大?。?/td> 0K
描述: IC ARM9 PHY 10/100MBPS 400-PBGA
標(biāo)準(zhǔn)包裝: 40
系列: KSZx692
應(yīng)用: 網(wǎng)絡(luò)和通信
核心處理器: ARM9
程序存儲(chǔ)器類型: 外部程序存儲(chǔ)器
控制器系列: KSZ
接口: EBI/EMI,以太網(wǎng),I²C,I²S,PCI,SPI,UART/USART,USB
輸入/輸出數(shù): 20
電源電壓: 1.235 V ~ 1.365 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 400-BGA
包裝: 托盤(pán)
供應(yīng)商設(shè)備封裝: 400-PBGA(24x24)
產(chǎn)品目錄頁(yè)面: 1080 (CN2011-ZH PDF)
其它名稱: 576-3537
Micrel, Inc.
KSZ8692MPB/KSZ8692XPB
March 2010
29
M9999-031810-4.0
Pin Number
Pin Name
Pin Type
Pin Description
D4
GNT2N
O
PCI Bus Grant 2
Assert Low.
In Host Bridge Mode, this is an output signal from the internal PCI arbiter to
grant PCI bus access to the master driving REQ2N.
In Guest Bridge Mode, this is unused.
(No connect for KSZ8692XPB)
B1
GNT1N
O
PCI Bus Grant 1
Assert Low.
In Host Bridge Mode, this is an output signal from the internal PCI arbiter to
grant PCI bus access to the master driving REQ1N.
In Guest Bridge Mode, this is an output signal to indicate to the external PCI
bus arbiter that KSZ8692MPB/KSZ8692XPB is requesting access to the PCI
bus.
D3
REQ3N
I
PCI Bus Request 3
Assert Low.
In Host Bridge Mode, this is an input signal from the external PCI device to
request for PCI bus access
In Guest Bridge Mode, this is unused.
(No connect for KSZ8692XPB)
E6
REQ2N
I
PCI Bus Request 2
Assert Low.
In Host Bridge Mode, this is an input signal from the external PCI device to
request for PCI bus access
In Guest Bridge Mode, this is unused.
(No connect for KSZ8692XPB)
C1
REQ1N
I
PCI Bus Request 1
Assert Low.
In Host Bridge Mode, this is an input signal from the external PCI device to
request for PCI bus access
In Guest Bridge Mode, this signal comes from the external arbiter to indicate
that the bus is granted to KSZ8692MPB/KSZ8692XPB.
B3, E7, D6,
A2, B4, A3,
D7, C5, C6,
B5, A4, A5,
B6, E8, C7,
D8, D10, B10,
A11, B11,
C11, A12,
E11, D11,
B12, A13,
C12, B13,
F12, C13,
D12, E12
PAD[31..0]
I/O
32-bit PCI address and data lines
Addresses and data bits are multiplexed on the same pins. During the first
clock cycle of a PCI transaction, the PAD bus contains the first clock cycle of a
PCI transaction, the PAD bus contains the physical address. During
subsequent clock cycles, these lines contain the 32-bit data to be transferred.
Depending upon the type of the transaction, the source of the data will be the
KSZ8692MPB/KSZ8692XPB if it initiates a PCI write transaction, or the data
source will be the target if it is a PCI Read transaction. The
KSZ8692MPB/KSZ8692XPB bus transaction consists of an address phase
followed by one or more data phases. The KSZ8692MPB/KSZ8692XPB
supports both Read and Write burst transactions. In case of a Read
transaction, a special data turn around cycle is needed between the address
phase and the data phase.
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