參數(shù)資料
型號(hào)： KSZ8031RNL-EVAL
廠商： Micrel Inc
文件頁(yè)數(shù)： 2/43頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR KSZ8031RNL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng) PHY
嵌入式： 否
已用 IC / 零件： KSZ8031RNL
已供物品： 板
相關(guān)產(chǎn)品： 576-3843-6-ND - TXRX PHY 100BASE TX 3.3V 24QFN
576-3843-1-ND - TXRX PHY 100BASE TX 3.3V 24QFN
576-3788-ND - TXRX PHY 10/100 3.3V 24-QFN
576-3843-2-ND - TXRX PHY 100BASE TX 3.3V 24QFN
576-3741-5-ND - TXRX PHY 100BASE TX 3.3V 24QFN
其它名稱： 576-3862
Micrel, Inc.
KSZ8021RNL / KSZ8031RNL
August 2010
10
M9999-082710-1.0
Pin Description – KSZ8021RNL / KSZ8031RNL (Continued)
Pin Number
Pin Name
Type
(1)
Pin Function
19
TXEN
I
RMII Transmit Enable Input
20
TXD0
I
RMII Transmit Data Input[0]
(3)
21
TXD1
I/O
RMII Transmit Data Input[1]
(3)
NAND Tree Mode:
NAND Tree output pin
22
GND
Gnd
Ground
23
LED0 /
ANEN_SPEED
Ipu/O
LED Output:
Programmable LED0 Output /
Config Mode:
Latched as Auto-Negotiation Enable (register 0h, bit [12]) and
SPEED (register 0h, bit [13]) at the de-assertion of reset. See
“Strapping Options” section for details.
The LED0 pin is programmable via register 1Fh bits [5:4], and is defined as follows.
LED mode = [00]
Link/Activity
Pin State
LED Definition
No Link
High
OFF
Link
Low
ON
Activity
Toggle
Blinking
LED mode = [01]
Link
Pin State
LED Definition
No Link
High
OFF
Link
Low
ON
LED mode = [10], [11]
Reserved
24
RST#
I
Chip Reset (active low)
PADDLE
GND
Gnd
Ground
Notes:
1.
P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin with internal pull-up (see Electrical
Characteristics for value) otherwise.
2.
RMII Rx Mode: The RXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each clock period in which CRS_DV is asserted,
two bits of recovered data are sent by the PHY to the MAC.
3.
RMII Tx Mode: The TXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock . For each clock period in which TXEN is asserted, two
bits of data are received by the PHY from the MAC.
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