參數(shù)資料
型號(hào)： KSZ8031RNL-EVAL
廠商： Micrel Inc
文件頁(yè)數(shù)： 11/43頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR KSZ8031RNL
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，以太網(wǎng) PHY
嵌入式： 否
已用 IC / 零件： KSZ8031RNL
已供物品： 板
相關(guān)產(chǎn)品： 576-3843-6-ND - TXRX PHY 100BASE TX 3.3V 24QFN
576-3843-1-ND - TXRX PHY 100BASE TX 3.3V 24QFN
576-3788-ND - TXRX PHY 10/100 3.3V 24-QFN
576-3843-2-ND - TXRX PHY 100BASE TX 3.3V 24QFN
576-3741-5-ND - TXRX PHY 100BASE TX 3.3V 24QFN
其它名稱： 576-3862
Micrel, Inc.
KSZ8021RNL / KSZ8031RNL
August 2010
19
M9999-082710-1.0
MII Management (MIIM) Interface
The KSZ8021/31RNL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input /
Output (MDIO) Interface. This interface enables upper-layer device, like a MAC processor, to monitor and control the state
of the KSZ8021/31RNL. An external device with MIIM capability is used to read the PHY status and/or configure the PHY
settings. Further details on the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification.
The MIIM interface consists of the following:
A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
A specific protocol that operates across the aforementioned physical connection that allows the external controller
to communicate with one or more PHY devices.
A set of 16-bit MDIO registers. Registers [0:8] are standard registers, and their functions are defined per the IEEE
802.3 Specification. The additional registers are provided for expanded functionality. See “Register Map” section
for details.
The KSZ8021/31RNL supports only two unique PHY addresses, 0x0h and 0x3h. The PHYAD[1:0] strapping pin is used to
select either 0x0h or 0x3h as the unique PHY address for the KSZ8021/31RNL device.
Table 3 shows the MII Management frame format for the KSZ8021/31RNL.
Preamble
Start of
Frame
Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA
Data
Bits [15:0]
Idle
Read
32 1’s
01
10
000AA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
000AA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
Table 3. MII Management Frame Format – for KSZ8021/31RNL
Interrupt (INTRP)
The INTRP (pin 18) is an optional interrupt signal that is used to inform the external controller that there has been a status
update to the KSZ8021/31RNL PHY register. Register 1Bh, bits [15:8] are the interrupt control bits to enable and disable
the conditions for asserting the INTRP signal. Register 1Bh, bits [7:0] are the interrupt status bits to indicate which
interrupt conditions have occurred. The interrupt status bits are cleared after reading register 1Bh.
Register 1Fh, bit 9 sets the interrupt level to active high or active low. The default is active low.
The MII management bus option gives the MAC processor complete access to the KSZ8021/31RNL control and status
registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.
HP Auto MDI/MDI-X
The HP Auto MDI/MDI-X configuration eliminates the confusion of whether to use a straight cable or a crossover cable
between the KSZ8021/31RNL and its link partner. This feature allows the KSZ8021/31RNL to use either type of cable to
connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive
pairs from the link partner, and then assigns transmit and receive pairs of the KSZ8021/31RNL accordingly.
HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a one to register 1Fh, bit [13]. MDI and MDI-X mode is
selected by register 1Fh, bit [14] if HP Auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support auto MDI/MDI-X.
The IEEE 802.3 Standard defines MDI and MDI-X in Table 4.
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