參數(shù)資料
型號: KSZ8031RNL-EVAL
廠商: Micrel Inc
文件頁數(shù): 16/43頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR KSZ8031RNL
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,以太網(wǎng) PHY
嵌入式:
已用 IC / 零件: KSZ8031RNL
已供物品:
相關(guān)產(chǎn)品: 576-3843-6-ND - TXRX PHY 100BASE TX 3.3V 24QFN
576-3843-1-ND - TXRX PHY 100BASE TX 3.3V 24QFN
576-3788-ND - TXRX PHY 10/100 3.3V 24-QFN
576-3843-2-ND - TXRX PHY 100BASE TX 3.3V 24QFN
576-3741-5-ND - TXRX PHY 100BASE TX 3.3V 24QFN
其它名稱: 576-3862
Micrel, Inc.
KSZ8021RNL / KSZ8031RNL
August 2010
23
M9999-082710-1.0
Slow Oscillator Mode
Slow Oscillator Mode is used to disconnect the input reference crystal/clock on XI (pin 8) and select the on-chip slow
oscillator when the KSZ8021/31RNL device is not in use after power-up. It is enabled by writing a one to register 11h, bit
[5].
Slow Oscillator Mode works in conjunction with Power Down Mode to put the KSZ8021/31RNL device in the lowest power
state with all internal functions disabled, except for the MII management interface. To properly exit this mode and return to
normal PHY operation, use the following programming sequence:
1. Disable Slow Oscillator Mode by writing a zero to register 11h, bit [5].
2. Disable Power Down Mode by writing a zero to register 0h, bit [11].
3. Initiate software reset by writing a one to register 0h, bit [15].
Reference Circuit for Power and Ground Connections
The KSZ8021/31RNL is a single 3.3V supply device with a built-in regulator to supply the 1.2V core. The power and
ground connections are shown in Figure 7 and Table 6 for 3.3V VDDIO.
Figure 7. KSZ8021/31RNL Power and Ground Connections
Power Pin
Pin Number
Description
VDD_1.2
1
Decouple with 2.2uF and 0.1uF capacitors-to-ground.
VDDA_3.3
2
Connect to board’s 3.3V supply through ferrite bead.
Decouple with 22uF and 0.1uF capacitors-to-ground.
VDDIO
14
Connect to board’s 3.3V supply for 3.3V VDDIO.
Decouple with 22uF and 0.1uF capacitors-to-ground.
Table 6. KSZ8021/31RNL Power Pin Description
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