參數(shù)資料
型號(hào): KS8993F
廠商: Micrel Inc
文件頁(yè)數(shù): 62/99頁(yè)
文件大?。?/td> 0K
描述: IC CONV MED 10/100 3PORT 128PQFP
標(biāo)準(zhǔn)包裝: 66
系列: *
類型: *
應(yīng)用: *
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
配用: KS8993F-EVAL-ND - EVAL KIT EXPERIMENTAL KS8993F
KS8993F
Micrel
August 26, 2004
Revision 1.0
- 65 -
4.3
Media Converter Registers
Register 64 (0x40): PHY Address
Bit
Name
R/W
Description
Defaul
t
7–5
Reserved
RO
N/A
000
4
Addr4
R/W
0
3
Addr3
R/W
0
2
Addr2
R/W
0
1
Addr1
R/W
0
Addr0
R/W
For Center side MC mode, these bits are port 1’s PHY address.
0 0000 : N/A
0 0001 : Port 1’s PHY address is 0x01h
0 0011 : Port 1’s PHY address is 0x03h
other values : N/A
For Terminal side MC mode, these bits are fixed at 0x01h for port 1’s
PHY address.
Notes
(1) If pins [MCHS,MCCS] = [0,1], a write to these bits with port 1’s
PHY address is required to enable port 1 and start the Center
side MC.
(2) If pins [MCHS,MCCS] = [0,1], the MIIM bus can only access
port
1.
(3) If pins [MCHS, MCCS] != [0,1], the MIIM bus will access port 1
using PHY address 0x01h and port 2 using PHY address
0x02h.
1
Register 65 (0x41): Center Side Status
Bit
Name
R/W
Description
Defaul
t
7
BUSY
RO
1 = indicate MC loop back mode inprogress, or receive reply
frame/timeout is pending
0 = exclude the above situations
0
6
Vendor mode
R/W
1 = non special vendor mode
0 = special vendor mode (compare My & LNK Partner Vendor
Info = 0x009099h)
0
5–3
Reserved
RO
Reserved
000
2
Option b
R/W
1 = clear status bits S6 to S10 to zero on Terminal MC side
0 = normal operation – supporting option b
0
1
Option a
R/W
1 = disable “Indicate Center MC Condition” frame
0 = enable “Indicate Center MC condition” frame
0
Request
RO
1 = indicate change of status/value in registers # 0x50h, 0x51h,
0x58h, 0x59h, 0x5Dh, 0x5Eh, 0x5Fh. This bit is self-cleared after a
read.
0 = exclude the above situations
0
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