2C Slave Serial Bus Configuration In manage" />
參數(shù)資料
型號(hào): KS8993F
廠商: Micrel Inc
文件頁(yè)數(shù): 38/99頁(yè)
文件大小: 0K
描述: IC CONV MED 10/100 3PORT 128PQFP
標(biāo)準(zhǔn)包裝: 66
系列: *
類(lèi)型: *
應(yīng)用: *
安裝類(lèi)型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
配用: KS8993F-EVAL-ND - EVAL KIT EXPERIMENTAL KS8993F
KS8993F
Micrel
August 26, 2004
Revision 1.0
- 43 -
2.10.2 I
2C Slave Serial Bus Configuration
In managed mode, the KS8993F can be configured as an I
2C slave device. In this mode, an I2C master device
(external controller/CPU) has complete programming access to the KS8993F’s 128 registers. Programming access
includes the Global Registers, Port Registers, Media Converter Registers, Advanced Control Registers and indirect
access to the “Static MAC Table”, “VLAN Table”, “Dynamic MAC Table” and “MIB Counters”. The tables and counters
are indirectly accessed via registers 110 thru 120.
In I
2C slave mode, the KS8993F operates like other I2C slave devices. Addressing the KS8993F’s 8 bit registers is
similar to addressing Atmel’s AT24C02 EEPROM’s memory locations. Details of I
2C read/write operations and related
timing information can be found in the AT24C02 Datasheet.
Two fixed 8 bit device addresses are used to address the KS8993F in I
2C slave mode. One is for read; the other is for
write. The addresses are as follow:
1011_1111
<read>
1011_1110
<write>
The following is a sample procedure for programming the KS8993F using the I
2C slave serial bus:
1.
Enable I
2C slave mode by setting the KS8993F strap-in pins PS[1:0] (pins 100 and 101 respectively) to “01”.
2.
Power up the board and assert reset to the KS8993F. After reset, the “Start Switch” bit (register 1 bit 0) will be
set to ‘0’.
3.
Configure the desired register settings in the KS8993F, using the I
2C write operation.
4.
Read back and verify the register settings in the KS8993F, using the I
2C read operation.
5.
Write a ‘1’ to the “Start Switch” bit to start the KS8993F with the programmed settings.
Note: The “Start Switch” bit cannot be set to ‘0’ to stop the switch after an ‘1’ is written to this bit. Thus, it is
recommended that all switch configuration settings are programmed before the “Start Switch” bit is set to ‘1’.
Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and
“Power down” can be programmed after the switch has been started.
2.10.3 SPI Slave Serial Bus Configuration
In managed mode, the KS8993F can be configured as a SPI slave device. In this mode, a SPI master device (external
controller/CPU) has complete programming access to the KS8993F’s 128 registers. Programming access includes
the Global Registers, Port Registers, Media Converter Registers, Advanced Control Registers and indirect access to
the “Static MAC Table”, “VLAN Table”, “Dynamic MAC Table” and “MIB Counters”. The tables and counters are
indirectly accessed via registers 110 thru 120.
The KS8993F supports two standard SPI commands: ‘0000_0011’ for data read and ‘0000_0010’ for data write. SPI
multiple read and multiple write are also supported by the KS8993F to expedite register read back and register
configuration, respectively.
SPI multiple read is initiated when the master device continues to drive the KS8993F SPIS_N input pin (SPI Slave
Select signal) low after a byte (a register) is read. The KS8993F internal address counter will increment automatically
to the next byte (next register) after the read. The next byte at the next register address will be shifted out onto the
KS8993F SPIQ output pin. SPI multiple read will continue until the SPI master device terminates it by de-asserting the
SPIS_N signal to the KS8993F.
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