2C Master Serial Bus Configuration With an " />
參數(shù)資料
型號: KS8993F
廠商: Micrel Inc
文件頁數(shù): 37/99頁
文件大?。?/td> 0K
描述: IC CONV MED 10/100 3PORT 128PQFP
標(biāo)準(zhǔn)包裝: 66
系列: *
類型: *
應(yīng)用: *
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
配用: KS8993F-EVAL-ND - EVAL KIT EXPERIMENTAL KS8993F
KS8993F
Micrel
August 26, 2004
Revision 1.0
- 42 -
2.10.1 I
2C Master Serial Bus Configuration
With an additional I
2C (“2-wire”) EEPROM, the KS8993F can perform more advanced switch features like “broadcast
storm protection” and “rate control” without the need of an external processor.
For KS8993F I
2C Master configuration, the EEPROM stores the configuration data for register 0 to register 109 (as
defined in the KS8993F register map) with the exception of the “Read Only” status registers. After the de-assertion of
reset, the KS8993F will sequentially read in the configuration data for all 110 registers, starting from register 0. The
configuration access time (tprgm) is less than 15 ms, as depicted in the following figure.
Figure 7: KS8993F EEPROM Configuration Timing Diagram
....
RST_N
SCL
SDA
t
prgm<15 ms
The following is a sample procedure for programming the KS8993F with a pre-configured EEPROM:
1.
Connect the KS8993F to the EEPROM by joining the SCL and SDA signals of the respective devices. For the
KS8993F, SCL is pin 97 and SDA is pin 98.
2.
Enable I
2C master mode by setting the KS8993F strap-in pins, PS[1:0] (pins 100 and 101, respectively) to
“00”.
3.
Check to ensure that the KS8993F reset signal input, RST_N (pin 67), is properly connected to the external
reset source at the board level.
4.
Program the desired configuration data into the EEPROM.
5.
Place the EEPROM on the board and power up the board.
6.
Assert an active-low reset to the RST_N pin of the KS8993F. After reset is de-asserted, the KS8993F will
begin reading the configuration data from the EEPROM. The KS8993F will check that the first byte read from
the EEPROM is “93”.
If this value is correct, EEPROM configuration will continue.
If not, EEPROM
configuration access is denied and all other data sent from the EEPROM will be ignored by the KS8993F. The
configuration access time (tprgm) is less than 15 ms.
Note: For proper operation, check to ensure that the KS8993F PWRDN input signal (pin 36) is not asserted during
the
reset operation. The PWRDN input is active low.
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