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參數(shù)資料
| 型號： | KS8695X-EVAL |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 38/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL EXPERIMENT KS8695X |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 相關(guān)產(chǎn)品： | KS8695X-ND - IC SWITCH 10/100 5PORT 208PQFP |
| 其它名稱： | 576-1005 |
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KS8695X
Micrel
M9999-102604
8
October 2004
Pin Number
Pin Name
Type(1)
Pin Function
66
DATA6
I/O
External Data Bit.
67
DATA5
I/O
External Data Bit.
68
DATA4
I/O
External Data Bit.
69
DATA3
I/O
External Data Bit.
70
DATA2
I/O
External Data Bit.
71
DATA1
I/O
External Data Bit.
72
DATA0
I/O
External Data Bit.
73
VDD-IO
P
3.3V Digital I/O Circuitry V
DD.
74
VSS-IO
Gnd
Digital I/O V
SS.
75
ECSN2
O
External I/O Device Chip Select. Active Low.
76
ECSN1
O
External I/O Device Chip Select. Active Low.
77
ECSN0
O
External I/O Device Chip Select. Active Low.
78
EWAITN
I
External Wait. Active Low.
79
VDD-IO
P
3.3V Digital I/O Circuitry V
DD.
80
VSS-IO
Gnd
Digital I/O V
SS.
81
RCSN1
O
ROM/SRAM/FLASH Chip Select. Active Low.
82
RCSN0
O
ROM/SRAM/FLASH Chip Select. Active Low.
83
WRSTO
O
Watchdog Timer Reset Output.
84
TEST3
NC
This pin must be left as no connect.
85
EROEN/
O/I
ROM/SRAM/FLASH and External I/O Output Enable. Active Low. /WRSTO
WRSTPLS
Polarity Select.
86
ERWEN3/
O
External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
TICTESTENN
87
ERWEN2/
O
External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
TESTREQA
88
ERWEN1/
O
External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
TESTREQB
89
ERWEN0/
O
External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
TESTACK
90
VDD-CORE
P
1.8V Digital Core V
DD.
91
VSS-CORE
Gnd
Digital Core V
SS.
92
URXD
I
UART Receive Data.
93
UDTRN/
O
UART Data Terminal Ready. Active Low. /Debug Enable (factory test signal).
DBGENN
94
UTXD
O
UART Transmit Data.
Note:
1. Gnd = Ground.
P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
O/I = Output in normal mode; input pin during reset.
NC = No connect.
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