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參數(shù)資料
| 型號(hào)： | KS8695X-EVAL |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 16/39頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL EXPERIMENT KS8695X |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 相關(guān)產(chǎn)品： | KS8695X-ND - IC SWITCH 10/100 5PORT 208PQFP |
| 其它名稱： | 576-1005 |
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October 2004
23
M9999-102604
KS8695X
Micrel
Pin
Name
I/O Type(1)
Description
78
EWAITN
I
External wait: Active low. This signal is asserted when an external I/O device or a
ROM/SRAM/FLASH bank needs more access cycles than those defined in the
corresponding control register.
81
RCSN[1]
O
ROM/SRAM/FLASH chip select: Active low. The KS8695X can access up to two
82
RCSN[0]
external ROM/SRAM/FLASH memory banks. The RCSN pins can be controlled to
map the CPU addresses into physical memory banks.
85
EROEN/
O/I
Normal mode: External I/O and ROM/SRAM/FLASH output enable: Active low.
WRSTPLS
When asserted, this signal controls the output enable port of the specified memory
device.
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, Active low;
WRSTPLS = 1, active high. No default.
89
ERWEN0/
O
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
TESTACK
the ERWENx controls the byte write enable of the memory device (except SDRAM).
ARM CPU test signal (factory test signal).
88
ERWEN1/
O
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
TESTREQB
the ERWENx controls the byte write enable of the memory device (except SDRAM).
ARM CPU test signal (factory test signal).
87
ERWEN2/
O
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
TESTREQA
the ERWENx controls the byte write enable of the memory device except SDRAM).
ARM CPU test signal (factory test signal).
86
ERWEN3/
O
External I/O and ROM/SRAM/FLASH write byte enable. Active low. When asserted,
TICTESTENN
the ERWENx controls the byte write enable of the memory device (except SDRAM).
ARM CPU test signal (factory test signal).
119
WLED0/
O/I
Normal mode: WAN LED indicator 0: Programmable via WAN misc. Control register
B0SIZE0
bits [2:0].
000 = Speed; 001 = Link; 010 = Full/half duplex; 011 = Collision;
100 = TX/RX activity; 101 = Full-duplex collision; 110 = Link/Activity.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
B0SiZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
118
WLED1/
O/I
Normal mode: WAN LED indicator 1: Programmable via WAN Misc. Control register
B0SIZE1
bits [6:4].
000 = Speed; 001 = Link; 010 = Full/half duplex; 011 = Collision;
100 = TX/RX activity; 101 = Full-duplex collision; 110 = Link/Activity.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
B0SIZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
Factory Test Pins
Pin
Name
I/O Type(1)
Description
117
TESTEN
I
Chip test enable: (factory test signal), pull down if not used.
197
TEST1
I
PHY test pin: (factory test signal).
149
TEST2
I
PHY test pin: (factory test signal).
Note:
1. I = Input.
O = Output.
O/I = Output in normal mode; input pin during reset.
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